K
K. Yanagisawa
Researcher at IBM
Publications - 2
Citations - 113
K. Yanagisawa is an academic researcher from IBM. The author has contributed to research in topics: Macro & Sense amplifier. The author has an hindex of 2, co-authored 2 publications receiving 109 citations.
Papers
More filters
Proceedings ArticleDOI
A 500MHz Random Cycle 1.5ns-Latency, SOI Embedded DRAM Macro Featuring a 3T Micro Sense Amplifier
John E. Barth,William Robert Reohr,Paul C. Parries,Gregory J. Fredeman,John W. Golz,Stanley E. Schuster,Richard E. Matick,Hillery C. Hunter,C. Tanner,J. Harig,Hyun-Chul Kim,Babar A. Khan,J. Griesemer,R.P. Havreluk,K. Yanagisawa,T. Kirihata,S. S. Iyer +16 more
TL;DR: A prototype SOI embedded DRAM macro is developed for high-performance microprocessors and introduces performance-enhancing 3T micro sense amplifier architecture (muSA), which confirms 1.5ns random access time with a 1V supply at 85deg and low voltage operation with a 600mV supply.
Journal ArticleDOI
A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier
John E. Barth,William Robert Reohr,Paul C. Parries,Gregory J. Fredeman,John W. Golz,Stanley E. Schuster,Richard E. Matick,Hillery C. Hunter,C. Tanner,J. Harig,Kim Hoki,Babar A. Khan,J. Griesemer,R.P. Havreluk,K. Yanagisawa,T. Kirihata,Subramanian S. Iyer +16 more
TL;DR: In this paper, the authors describe a 500 MHz random cycle silicon on insulator (SOI) embedded DRAM macro which features a three-transistor micro sense amplifier, achieving significant performance gains over traditional array design methods.