Learn the basic properties and designs of modern VLSI devices, as well as the factors affecting performance, with this thoroughly updated second edition. The first edition has been widely adopted as a standard textbook in microelectronics in many major US universities and worldwide. The internationally-renowned authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices. Equations and parameters provided are checked continuously against the reality of silicon data, making the book equally useful in practical transistor design and in the classroom. Every chapter has been updated to include the latest developments, such as MOSFET scale length theory, high-field transport model, and SiGe-base bipolar devices.

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Fundamentals of Modern VLSI Devices

The silicon-germanium heterojunction bipolar transistor (SiGe HBT) is the first practical bandgap-engineered device to be realized in silicon. SiGe HBT technology combines transistor performance competitive with III-V technologies with the processing maturity, integration levels, yield, and hence, cost commonly associated with conventional Si fabrication. In the ten-and-one-half years since the first demonstration of a functional transistor, SiGe HBT technology has emerged from the research laboratory, entered manufacturing on 200-mm wafers, and is poised to enter the commercial RF and microwave market. State-of-the-art SiGe HBT's can deliver: (1) f/sub T/ in excess of 50 GHz; (2) f/sub max/ in excess of 70 GHz; (3) minimum noise figure below 0.7 dB at 2.0 GHz; (4) 1/f noise corner frequencies below 500 Hz; (5) cryogenic operation; (6) excellent radiation hardness; (7) competitive power amplifiers; and (8) reliability comparable to Si. A host of record-setting digital, analog, RF, and microwave circuits have been demonstrated in the past several years using SiGe HBT's, and recent work on passives and transmission lines on Si suggest a migratory path to Si-based monolithic microwave integrated circuits (MMIC's) is possible. The combination of SiGe HBT's with advanced Si CMOS to form an SiGe BiCMOS technology represents a unique opportunity for Si-based RF system-on-a-chip solutions. This paper reviews state-of-the-art SiGe HBT technology and assesses its potential for current and future RF and microwave systems.

SiGe HBT technology: a new contender for Si-based RF and microwave circuit applications

Advanced epitaxial growth techniques permit the use of pseudomorphic Si/sub 1-x/Ge/sub x/ alloys in silicon technology. The smaller bandgap of these alloys allows for a variety of novel band-engineered structures that promise to enhance silicon-based technology significantly. The authors discuss the growth and properties of pseudomorphic Si/sub 1-x/Ge/sub x/ structures and then focus on their applications, especially the Si/sub 1-x/Ge/sub x/-base heterojunction bipolar transistor (HBT). They show that HBTs in the Si/sub 1-x/Ge/sub x/ system allow for the decoupling of current gain and intrinsic base resistance. Such devices can be made by using a variety of techniques, including molecular-beam epitaxy and chemical vapor deposition. The authors describe the evolution of fabrication schemes for such HBTs and describe the DC and AC results obtained. They show that optimally designed HBTs coupled with advanced bipolar structures can provide performance leverage. >

Heterojunction bipolar transistors using Si-Ge alloys

Metal silicides have played an indispensable role in the rapid developments of microelectronics since PtSi was first used to improve the rectifying characteristics of diodes in early 1960s. This wo ...

Metal silicides in CMOS technology : Past, present, and future trends

Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are present in certain regions of the strained material layers, there is degradation in device performance. By employing semiconductor structures and devices (e.g., field effect transistors or “FETs”) that have the features described, or are fabricated in accordance with the steps described, device operation is enhanced.

Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same

Demonstrating a >10X density increase over traditional VLSI fuse circuits, a compact eFUSE programmable array memory configured as a 4 Kb one-time programmable ROM (OTPROM) is presented using a 6.2 mum2 NiSix silicide electromigration ITIR cell in 65 nm SOI CMOS. A 20 mus programming time at 1.5 V is achieved by asymmetrical scaling of the fuse and a shared differential sensing scheme. Having zero process cost adder, eFUSE is fully compatible with standard VLSI manufacturing.

A Compact eFUSE Programmable Array Memory for SOI CMOS

The evolution of interfacial reactions during the deposition of Pt and Pd on epitaxial Si1−xGex alloys was studied using x‐ray photoelectron spectroscopy (XPS) for metal coverage up to 10 A. Auger electron depth profiling was performed on a thicker metal overlayer before and after in vacuo annealing to study the redistribution of composition in the reactions. We have found that Pt and Pd react mainly with Si to form silicides at 350 °C, leaving some Ge to segregate at the surface. These results were correlated with Schottky barrier height measurements. We found that the Schottky barrier heights of Pt/n‐Si0.8Ge0.2 and Pd/n‐Si0.8Ge0.2 are about the same, pinned at 0.68 eV, which is much smaller than those of n‐Si. These barrier heights are quite stable up to 550 °C.

Interfacial reactions and Schottky barriers of Pt and Pd on epitaxial Si1-xGex alloys

The reliability of NiPtSi/p-poly Si electrical fuses with different programming mechanisms, i.e., electromigration and thermal rupture, was investigated in terms of fuse resistance stability and fuse array functionality for the 65-nm technology node. The resistance of the fuses programmed within the electromigration programming window was found to be very stable; resistance shift was only observed on fuses programmed in the underprogrammed mode, which results in incomplete electromigration. For fuses programmed with the thermal rupture mechanism, both resistance shift and functional sensing fails were observed. Furthermore, a guard band was defined for fuses programmed with an electromigration mechanism to ensure sufficient margins for fuse reliability. However, a guard band cannot be defined for fuses programmed with a rupture mode due to the unpredictable nature of the rupture programming mechanism. The unprogrammed fuse elements were shown to be stable through extensive reliability evaluations.

Reliability investigation of NiPtSi electrical fuse with different programming mechanisms

A prototype SOI embedded DRAM macro is developed for high-performance microprocessors and introduces performance-enhancing 3T micro sense amplifier architecture (muSA). The macro was characterized via a test chip fabricated in a 65nm SOI deep-trench DRAM process. Measurements confirm 1.5ns random access time with a 1V supply at 85deg and low voltage operation with a 600mV supply.

S. S. Iyer

Papers

A Compact eFUSE Programmable Array Memory for SOI CMOS

Interfacial reactions and Schottky barriers of Pt and Pd on epitaxial Si1-xGex alloys

Reliability investigation of NiPtSi electrical fuse with different programming mechanisms

A 500MHz Random Cycle 1.5ns-Latency, SOI Embedded DRAM Macro Featuring a 3T Micro Sense Amplifier

Silicon-Germanium-Base Heteroiunction BiPolar Transistors By Molecular Biam Epitax;