P
Paul C. Parries
Researcher at IBM
Publications - 73
Citations - 1295
Paul C. Parries is an academic researcher from IBM. The author has contributed to research in topics: Dram & Trench. The author has an hindex of 21, co-authored 73 publications receiving 1275 citations. Previous affiliations of Paul C. Parries include GlobalFoundries.
Papers
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Proceedings ArticleDOI
22nm High-performance SOI technology featuring dual-embedded stressors, Epi-Plate High-K deep-trench embedded DRAM and self-aligned Via 15LM BEOL
Shreesh Narasimha,Paul Chang,Claude Ortolland,David M. Fried,E. Engbrecht,Karen A. Nummy,Paul C. Parries,Takashi Ando,Michael V. Aquilino,N. Arnold,R. Bolam,Jin Cai,Michael P. Chudzik,Benjamin Cipriany,G. Costrini,Min Dai,Jessica Dechene,C. DeWan,Bernard A. Engel,Michael A. Gribelyuk,Dechao Guo,G. Han,N. Habib,Judson R. Holt,Dimitris P. Ioannou,Basanth Jagannathan,Jaeger Daniel,J. Johnson,W. Kong,J. Koshy,Rishikesh Krishnan,Amit Kumar,Mahender Kumar,Jae Gon Lee,Xiaolin Li,C-H. Lin,Barry P. Linder,S. Lucarini,Naftali E. Lustig,Paul S. McLaughlin,Katsunori Onishi,Viorel Ontalus,Robert R. Robison,Christopher D. Sheraw,Matthew W. Stoker,Alvin G. Thomas,Geng Wang,Richard Wise,L. Zhuang,Gregory G. Freeman,J. Gill,Edward P. Maciejewski,Rajeev Malik,J. Norum,Paul D. Agnello +54 more
TL;DR: A hierarchical BEOL with 15 levels of copper interconnect including self-aligned via processing delivers high performance with exceptional reliability in SOI CMOS 22nm technology.
Journal ArticleDOI
Embedded DRAM: technology platform for the Blue Gene/L chip
TL;DR: The salient features of this 130-nm complementary metal oxide semiconductor technology, including the IBM unique embedded dynamic random access memory (DRAM) technology, are outlined.
Patent
Method for providing silicide bridge contact between silicon regions separated by a thin dielectric
TL;DR: In this paper, a silicide bridge is constructed by selectively growing over exposed silicon regions under conditions that provide controlled lateral growth over the thin dielectric without also permitting lateral growth on other insulator regions.
Proceedings Article
A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier
John E. Barth,William Robert Reohr,Paul C. Parries,Gregory J. Fredeman,John W. Golz,Stanley E. Schuster,Richard E. Matick,Hillery C. Hunter,Charles C. Tanner,Joseph Harig,Hoki Kim,Babar A. Khan,John Griesemer,Robert P. Havreluk,Kenji Yanagisawa,Toshiaki Kirihata,Subramanian S. Iyer +16 more
TL;DR: In this article, the authors describe a 500MHz random cycle Silicon on Insulator (SOI) embedded DRAM macro which features a three-transistor micro sense amplifier, realizing significant performance gains over traditional array design methods.
Journal ArticleDOI
An 800-MHz embedded DRAM with a concurrent refresh mode
T. Kirihata,Paul C. Parries,David R. Hanson,Hoki Kim,John W. Golz,Gregory J. Fredeman,R. Rajeevakumar,J. Griesemer,Norman Robson,Alberto Cestero,Babar A. Khan,Geng Wang,M. Wordeman,Subramanian S. Iyer +13 more
TL;DR: An 800-MHz embedded DRAM macro employs a memory cell utilizing a device from the 90-nm high-performance technology menu; a 2.2-nm gate oxide 1.5 V IO device to improve the memory utilization to over 99% for a 64 /spl mu/s data retention time.