Over the last decade, gallium nitride (GaN) has emerged as an excellent material for the fabrication of power devices. Among the semiconductors for which power devices are already available in the market, GaN has the widest energy gap, the largest critical field, and the highest saturation velocity, thus representing an excellent material for the fabrication of high-speed/high-voltage components. The presence of spontaneous and piezoelectric polarization allows us to create a two-dimensional electron gas, with high mobility and large channel density, in the absence of any doping, thanks to the use of AlGaN/GaN heterostructures. This contributes to minimize resistive losses; at the same time, for GaN transistors, switching losses are very low, thanks to the small parasitic capacitances and switching charges. Device scaling and monolithic integration enable a high-frequency operation, with consequent advantages in terms of miniaturization. For high power/high-voltage operation, vertical device architectures are being proposed and investigated, and three-dimensional structures—fin-shaped, trench-structured, nanowire-based—are demonstrating great potential. Contrary to Si, GaN is a relatively young material: trapping and degradation processes must be understood and described in detail, with the aim of optimizing device stability and reliability. This Tutorial describes the physics, technology, and reliability of GaN-based power devices: in the first part of the article, starting from a discussion of the main properties of the material, the characteristics of lateral and vertical GaN transistors are discussed in detail to provide guidance in this complex and interesting field. The second part of the paper focuses on trapping and reliability aspects: the physical origin of traps in GaN and the main degradation mechanisms are discussed in detail. The wide set of referenced papers and the insight into the most relevant aspects gives the reader a comprehensive overview on the present and next-generation GaN electronics.

https://hal.archives-ouvertes.fr/hal-03421528/document

GaN-based power devices: Physics, reliability, and perspectives

Two-dimensional crystals have emerged as a class of materials that may impact future electronic technologies. Experimentally identifying and characterizing new functional two-dimensional materials is challenging, but also potentially rewarding. Here, we fabricate field-effect transistors based on few-layer black phosphorus crystals with thickness down to a few nanometres. Reliable transistor performance is achieved at room temperature in samples thinner than 7.5 nm, with drain current modulation on the order of 10(5) and well-developed current saturation in the I-V characteristics. The charge-carrier mobility is found to be thickness-dependent, with the highest values up to ∼ 1,000 cm(2) V(-1) s(-1) obtained for a thickness of ∼ 10 nm. Our results demonstrate the potential of black phosphorus thin crystals as a new two-dimensional material for applications in nanoelectronic devices.

http://absimage.aps.org/image/MAR14/MWS_MAR14-2013-005031.pdf

Black Phosphorus Field-effect Transistors

Gallium nitride (GaN) power devices enable power electronic systems with enhanced power density and efficiency. Dynamic on-resistance ( $R_{\mathrm{\scriptscriptstyle ON}}$ ) degradation (or current collapse), originating from buffer trapping, surface trapping and gate instability, has been regarded as a primary challenge for the lateral GaN-on-Si power devices. In this paper, we present an overview and discussion of the mechanisms, characterizations, modeling, and solutions for the degradation of dynamic $R_{\mathrm{\scriptscriptstyle ON}}$ in GaN power devices. The complex dynamics of acceptor/donor buffer traps and their impacts on dynamic $R_{\mathrm{\scriptscriptstyle ON}}$ have been analyzed and revealed by TCAD simulations and high-voltage back-gating measurements. The gate instability-induced dynamic $R_{\mathrm{\scriptscriptstyle ON}}$ increase in different GaN device technologies and the role of gate overdrive are also discussed. Wafer-level and board-level characterization techniques enabling accurate dynamic $R_{\mathrm{\scriptscriptstyle ON}}$ evaluation are reviewed. The dynamic $R_{\mathrm{\scriptscriptstyle ON}}$ performance of the state-of-the-art commercial GaN devices is presented, and a behavioral model with the dynamic $R_{\mathrm{\scriptscriptstyle ON}}$ degradation taken into consideration has been implemented for circuit analysis. The latest progress in GaN device technologies for enhanced dynamic performance is also reviewed and discussed.

Dynamic On-Resistance in GaN Power Devices: Mechanisms, Characterizations, and Modeling

In this paper, we carried out a systematic investigation on gate degradation and the physical mechanism of the Schottky-type ${p}$ -GaN gate HEMTs under positive gate voltage stress. The frequency- and temperature-dependent measurements have been conducted. It is found that the time-dependent gate degradation exhibits weak relevance with frequencies ranging from 10 to 100 kHz under dynamic gate stress and is similar to that in static gate stress. Both the gate breakdown voltage (BV) and mean-time-to-failure (MTTF) show positive temperature dependence. Moreover, the current–voltage ( I–V ) characteristics and threshold voltage ( ${V}_{\text {TH}}$ ) instability of ${p}$ -GaN devices before/after gate degradation are compared and analyzed. The degraded Schottky junction exhibits an ohmic-like gate behavior. It is revealed that under a large gate bias stress, high-energy electrons accelerated in the depletion region of the ${p}$ -GaN layer would promote the formation of defect levels near the metal/ ${p}$ -GaN interface, leading to the initial ${p}$ -GaN layer degradation. The subsequent high gate leakage density could cause the final degradation of the AlGaN barrier.

Frequency- and Temperature-Dependent Gate Reliability of Schottky-Type ${p}$ -GaN Gate HEMTs

GaN technology is not only gaining traction in power and RF electronics but is also rapidly expanding into other application areas including digital and quantum computing electronics. This paper provides a glimpse of future GaN device technologies and advanced modeling approaches that can push the boundaries of these applications in terms of performance and reliability. While GaN power devices have recently been commercialized in the 15–900 V classes, new GaN devices are greatly desirable to explore both higher-voltage and ultra-low-voltage power applications. Moving into the RF domain, ultra-high frequency GaN devices are being used to implement digitized power amplifier circuits, and further advances using the hardware–software co-design approach can be expected. On the horizon is the GaN CMOS technology, a key missing piece to realize the full-GaN platform with integrated digital, power, and RF electronics technologies. Although currently a challenge, high-performance p-type GaN technology will be crucial to realize high-performance GaN CMOS circuits. Due to its excellent transport characteristics and ability to generate free carriers via polarization doping, GaN is expected to be an important technology for ultra-low temperature and quantum computing electronics. Finally, given the increasing cost of hardware prototyping of new devices and circuits, the use of high-fidelity device models and data-driven modeling approaches for technology-circuit co-design are projected to be the trends of the future. In this regard, physically inspired, mathematically robust, less computationally taxing, and predictive modeling approaches are indispensable. With all these and future efforts, we envision GaN to become the next Si for electronics.

Emerging GaN technologies for power, RF, digital, and quantum computing applications: Recent advances and prospects

The drain induced dynamic threshold voltage ( ${V}_{\textrm {th}}$ ) shift of a ${p}$ -GaN gate HEMT with a Schottky gate contact is investigated, and the underlying mechanisms are explained with a charge storage model. When the device experiences a high drain bias ${V}_{\textrm {DSQ}}$ , the gate-to-drain capacitance ( ${C}_{\textrm {GD}}$ ) is charged to ${Q}_{\textrm {GD}}$ ( ${V}_{\textrm {DSQ}}$ ). As the drain voltage drops to ${V}_{\textrm {DSM}}$ where ${V}_{\textrm {th}}$ is measured, ${C}_{\textrm {GD}}$ is expected to be discharged to ${Q}_{\textrm {GD}}$ ( ${V}_{\textrm {DSM}}$ ). However, the metal/ ${p}$ -GaN Schottky junction could block the discharging current, resulting in storage of negative charges in the ${p}$ -GaN layer. For the device to turn on, additional gate voltage is required to counteract the stored negative charges, resulting in a positive shift of ${V}_{\textrm {th}}$ . The dynamic ${V}_{\textrm {th}}$ shift is an intrinsic and predictable characteristic of the ${p}$ -GaN gate HEMT which is linearly correlated with $\Delta \!{Q}_{\textrm {GD}}={Q}_{\textrm {GD}}$ ( ${V}_{\textrm {DSQ}}$ ) $- {Q}_{\textrm {GD}}$ ( ${V}_{\textrm {DSM}}$ ). The ${V}_{\textrm {th}}$ shift is dependent on ${V}_{\textrm {DSQ}}$ as well as ${V}_{\textrm {DSM}}$ , indicating that the ${V}_{\textrm {th}}$ shift is varying along the load line during a switching operation.

Charge Storage Mechanism of Drain Induced Dynamic Threshold Voltage Shift in ${p}$ -GaN Gate HEMTs

Various 2D/3D heterostructures can be created by harnessing the advantages of both the layered two-dimensional semiconductors and bulk materials. A semiconducting gate field-effect transistor (SG-FET) structure based on 2D/3D heterostructures is proposed here. The SG-FET is demonstrated on an AlGaN/GaN high-electron mobility transistor (HEMT) by adopting single-layer MoS2 as the gate electrode. The MoS2 semiconducting gate can effectively turn on and turn off the HEMT without sacrificing the subthreshold swing and breakdown voltage. Most importantly, the proposed semiconducting gate can deliver inherent over-voltage protection for field-effect transistors (FETs). Furthermore, the self-adjustable semiconducting gate potential with drain bias can even boost the ON-current while guaranteeing the safe operation of FET. In implementing the semiconducting gate, the layered two-dimensional materials such as the adopted MoS2 have several important benefits such as the feasibility of high-quality crystals on different gate dielectrics and the good controllability of semiconducting gate depletion threshold voltage by the layer thickness. The demonstrated semiconducting gate as over-voltage protection for HEMT can be extended to other FETs, which can become another advantageous arena for the possible applications of the layered two-dimensional materials.

/pdf/2d-materials-as-semiconducting-gate-for-field-effect-22lraegh0f.pdf

2D materials as semiconducting gate for field-effect transistors with inherent over-voltage protection and boosted ON-current

The dynamics of the intrinsic threshold voltage ( ${V}_{{\text {TH}}}{)}$ shift in 650-V Schottky-type p-GaN gate HEMT under high-frequency switching is investigated by a bootstrap voltage clamping circuit in which the GaN HEMT serves as the key bootstrapping device. This new testing setup covers a wide range of OFF-state drain bias ( ${V}_{{\text {DSQ}}}{)}$ up to 400V, a short OFF-to-ON (or stress-to-sense) delay ( ${T}_{{\text {delay}}}{)}$ of 60ns, and a high switching frequency ( ${f}_{{\text {sw}}}{)}$ up to 2MHz. The dynamic ${V}_{{\text {TH}}}$ ’s dependences on ${V}_{{\text {DSQ}}}$ and ${f}_{{\text {sw}}}$ are characterized by this testing setup. A higher VDSQ (up to 400V) results in a larger dynamic ${V}_{{\text {TH}}}$ shift ( $\Delta {V}_{{\text {TH}}}{)}$ . The $\Delta {V}_{{\text {TH}}}$ exhibits a gradually increasing trend under the continuous high-frequency switching mode. In addition, after continuous switching operation for $200\mu \text{s}$ , the maximum $\Delta {V}_{{\text {TH}}}$ shows no ${f}_{{\text {sw}}}$ dependence with a wide range of frequency from 50kHz to 2MHz.

Characterization of Dynamic Threshold Voltage in Schottky-Type p -GaN Gate HEMT Under High-Frequency Switching

The $p$ -GaN gate HEMT with a Schottky gate contact is studied in this work. The threshold voltage ( $\boldsymbol{V}_{\mathbf{th}}$ ) of the device is found to have a dynamic nature. When the device experiences a high drain voltage $V_{\text{DSQ}}$ , the gate-to-drain capacitance $C_{\text{GD}}$ is charged to $\boldsymbol{Q}_{\mathbf{GD}}(\boldsymbol{V}_{\mathbf{DSQ}})$ . The negative part of $\boldsymbol{Q}_{\mathbf{GD}}(\boldsymbol{V}_{\mathbf{DSQ}})$ is mainly located in the $p$ -GaN layer. When drain voltage drops to a lower value $V_{\text{DSM}}$ , the non-equilibrium charges $\Delta \boldsymbol{Q}_{\mathbf{GD}}=\boldsymbol{Q}_{\mathbf{GD}}(\boldsymbol{V}_{\mathbf{GDQ}})-\boldsymbol{Q}_{\mathbf{GD}}(\boldsymbol{V}_{\mathbf{GDM}})$ cannot be effectively released, since the discharging current is blocked by the reversely biased metal/ $p$ -GaN Schottky junction and $\boldsymbol{p}$ -GaN/2DEG PN junction. An extra $V_{\text{GS}}$ is required to counteract the non-equilibrium $\Delta \boldsymbol{Q}_{\mathbf{GD}}$ , resulting in a change of $\boldsymbol{V}_{\mathbf{th}}$ . The change in $\boldsymbol{V}_{\mathbf{th}}$ is well predictable by its linear relationship to $\Delta \boldsymbol{Q}_{\mathbf{GD}}$ . During switching operation, $\boldsymbol{V}_{\mathbf{th}}$ is adaptive along the load line. Without considering the dynamic $\boldsymbol{V}_{\mathbf{th}}$ effect, there exist large discrepancies in switching transients between the modelled and the experimental results. Incorporation of the dynamic $\boldsymbol{V}_{\mathbf{th}}$ in device model result in greatly enhanced accuracy in simulated transient behavior.

Kailun Zhong

Papers

Charge Storage Mechanism of Drain Induced Dynamic Threshold Voltage Shift in ${p}$ -GaN Gate HEMTs

Frequency- and Temperature-Dependent Gate Reliability of Schottky-Type ${p}$ -GaN Gate HEMTs

2D materials as semiconducting gate for field-effect transistors with inherent over-voltage protection and boosted ON-current

Characterization of Dynamic Threshold Voltage in Schottky-Type p -GaN Gate HEMT Under High-Frequency Switching

Dynamic Threshold Voltage in $p$ -GaN Gate HEMT