Kamalesh Hatua

TL;DR: In this article, the authors proposed an active gate driving technique for SiC MOSFETs to improve overall switching performance in the presence of parasitic inductance in the converter layout.

TL;DR: In this article, the switching behavior of a 1200V, 35 A, SiC MOSFET is tested extensively in different parasitic condition. And a limiting value of these inductances is provided to build a voltage source inverter with SiC mOSFet utilizing its full switching potential.

TL;DR: In this paper, the authors proposed an active gate driving technique for SiC mosfet to improve its overall switching performance in the presence of a moderately higher amount of parasitic inductance in the converter layout.

TL;DR: In this article, the harmonic performance and current distortion of the grid-connected, three-level neutral point clamped converter using 15 kV silicon carbide Insulated Gate Bipolar Transistor (IGBTs) are investigated.

Abstract: The ultrahigh voltage (> 12 kV) SiC IGBTs are promising power semiconductor devices for medium voltage power conversion due to feasibility of simple two-level topologies, reduced component count and extremely high efficiency. However, the current devices generate high dv/dt during switching transitions because of the deep punch-through design. This paper investigates the behavior of dv/dt during the two-slope (different slopes before and after punch-through) turn-on and turn-off voltage transitions of these devices, by varying the device current, temperature and field-stop buffer layer design. It is shown that the dv/dt can be minimized by increasing the gate resistance, by taking the turn-on transition as reference. However, it is found that the increase in gate resistance has very weak impact on dv/dt above the punch-through voltage, and also resulting in significantly increased switching energy loss. It is shown that this problem can be addressed by using a two-stage active gate driver, where the gate current is appropriately controlled to limit the dv/dt over punch-through voltage and to minimize the switching energy loss under the punch-through voltage. Experimental results on 15 kV SiC N-IGBTs with field-stop buffer layer thickness of 2 μm and 5 μm are presented up to 11 kV with a detailed discussion of the results.