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Kees Goossens

Researcher at Eindhoven University of Technology

Publications -  280
Citations -  8474

Kees Goossens is an academic researcher from Eindhoven University of Technology. The author has contributed to research in topics: Network on a chip & System on a chip. The author has an hindex of 45, co-authored 270 publications receiving 8198 citations. Previous affiliations of Kees Goossens include Synopsys & Delft University of Technology.

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Journal ArticleDOI

AEthereal network on chip: concepts, architectures, and implementations

TL;DR: The AEthereal NoC is introduced, which provides guaranteed services (GSs) - such as uncorrupted, lossless, ordered data delivery; guaranteed throughput; and bounded latency - are essential for the efficient construction of robust SoCs and exploits the NoC capacity unused by the GS traffic.
Proceedings ArticleDOI

Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip

TL;DR: In this article, the guaranteed throughput (GT) and best-effort (BE) routers are combined in an efficient implementation by sharing resources, and the trade offs between hardware complexity and efficiency of the combined router are discussed.
Proceedings ArticleDOI

Predator: a predictable SDRAM memory controller

TL;DR: In this article, the authors present a memory controller design that provides a guaranteed minimum bandwidth and a maximum latency bound to the IPs, which is accomplished using a novel two-step approach to predictable SDRAM sharing.
Journal ArticleDOI

CoMPSoC: A template for composable and predictable multi-processor system on chips

TL;DR: A Composable and Predictable Multi-Processor System on Chip (CoMPSoC) platform template is proposed, which enables a divide-and-conquer design strategy, where all applications, potentially using different programming models and communication paradigms, are developed and verified independently of one another.
Proceedings ArticleDOI

A Design Flow for Application-Specific Networks on Chip with Guaranteed Performance to Accelerate SOC Design and Verification

TL;DR: An operational design flow is described that generates and configures application-specific network on chip (NOC) instances, given application communication requirements, that are guaranteed to meet the application's communication requirements in minutes.