Introduction to Electromagnetic Compatibility

High-frequency power converters enabled by wide bandgap (WBG) and silicon semiconductor devices offer distinct advantages in power density and dynamic performance. However, switching oscillations are commonly observed in these circuits with undesirable consequences. This paper reviews the impacts, root causes, and mitigation techniques of switching oscillations through literature survey, modeling analysis, and experimental investigation. We categorize the following root causes for oscillations during switching transients: 1) damped oscillation triggered by high di/dt and/or dv/dt coupled with parasitic elements; 2) undamped oscillation of WBG devices as part of a negative resistance oscillator; and 3) semiconductor device physical mechanisms such as the negative capacitance phenomenon due to conductivity modulation in insulated gate bipolar transistors or impact ionization in MOSFETs, the plasma extraction transit-time effect in bipolar power devices, and the reverse conduction property of GaN HEMTs. Furthermore, this paper discusses various circuit techniques to suppress switching oscillations, and techniques of extracting parasitic inductances of power devices.

A Survey on Switching Oscillations in Power Converters

A novel de-embedding method on transmission line device under testing (DUT) is introduced in this paper. The technique can be used as an alternative to classic calibration approaches, such as SOLT, TRL, LRM, or LRRM whenever the de-embedded structure is a transmission line. The method only requires two measurement patterns: a true through as test fixture and a total pattern with targeting DUT embedded in. With a quasi-symmetry requirement in test fixtures, it is also a good substitute for newly released two-pattern de-embedding methodologies which have rigid symmetric demanding in text fixtures design and manufactures.

A novel de-embedding method suitable for transmission-line measurement

Electrical properties of dielectric substrate are critical in designing high-speed products in terms of signal and power integrity. It is important to accurately characterize the dielectric properties to avoid overestimating or underestimating in the design. This paper proposes the improved “Root-Omega” method for extracting dielectric properties from fabricated multilayer printed circuit boards. Based on the electrical properties of fabricated transmission lines, the improved “Root-Omega” method applied to cases with smooth and rough conductors is validated using simulations. Error sensitivity analysis is performed to demonstrate the potential errors in the original “Root-Omega” procedure and the error sensitivity is significantly reduced by the proposed improvements.

Improved “Root-Omega” Method for Transmission-Line-Based Material Property Extraction for Multilayer PCBs

Because of the simplicity of design and measurement, as well as the accuracy of results, the 2×-thru de-embedding has replaced the traditional de-embedding algorithms such as thru-reflect-line and short-open-load-thru for printed circuit board (PCB) characterization. In this paper, the theory of [$2^{n}$ -port 2×-Thru de-embedding is derived first. The self-error reduction schemes are introduced to mitigate the de-embedding errors due to non-ideal manufacturing effects that make mode conversion terms non-zero. Both the theory and the self-error reduction schemes are fully validated through simulation and measurement cases.

Multi-Ports ( [$2^{n}$ ) 2×-Thru De-Embedding: Theory, Validation, and Mode Conversion Characterization

Signal integrity (SI) and power integrity (PI) modelling and design require accurate knowledge of dielectric properties of printed circuit board (PCB) laminate dielectrics. Dielectric properties of a laminate dielectric can be obtained from a set of the measured S-parameters on a PCB stripline with a specially designed through-reflect-line (TRL) calibration pattern. In this work, it is proposed to extract dielectric properties from the measurements of S-parameters on the two 50-Ohm stripline structures of the same length, but different widths of the trace, designed on the same layer of a PCB. The dielectric properties on these two lines should be identical. However, an application of the simplest "root-omega" technique to extract dielectric properties of the substrate would lead to the ambiguity in the extracted data. This is because the conductor surface roughness affects the measured S-parameters and is lumped in the extracted dielectric data. This problem of ambiguity in the dielectric properties extraction can be overcome using the approach analogous to the recently proposed method to separate dielectric and conductor losses on PCB lines with different widths and roughness profiles (1).

Characterization of PCB Dielectric Properties Using Two Striplines on the Same Board

This paper presents the design of serial chip-to-chip communication at 20 Gbps including modeling and correlation for PCBs (Printed Circuit Boards) with FR4 substrate materials. The entire channel under investigation includes two packages, a 21-layer ceramic and a 12-layer organic, and a 22-layer PCB. A probing station, microprobes and a VNA are used to measure the entire channel S-parameters and the measurement is correlated to the simulation up to 20 GHz. Extended study for the channel with low loss PCB substrate material is simulated. Time-domain eye comparisons for the FR4 channel, low loss channel, and the FR4 channel with equalization are given. A general design rule as well as new technologies for the high-speed channel design at 20 Gbps and beyond are discussed and given in the conclusion.

Design and modeling for chip-to-chip communication at 20 Gbps

The ball grid array (BGA) structure is the interconnection between package to printed circuit board and the discontinuity from BGA affects the performance for the whole link path in the high-speed digital system. So, it is important to accurately model the BGA structures. In current methods, the current distribution of conductors is treated as isotropic. However, the pitch size of solder balls is comparable to the diameter. The current is no longer uniformly distributed. In this paper, a fast modal-based approach is developed to accurately and efficiently capture the proximity effect. Image theory is also applied in the proposed approach to reduce the computational domain from 3-D structure to 2-D. The matrix reduction approach is applied to obtain the physical loop inductance. The lumped capacitance is obtained in [1] . A $\pi $ topology equivalent circuit model for the BGA structure is built. Good agreement between the equivalent circuit model and full-wave simulation can be achieved up to 40 GHz.

Analytical Equivalent Circuit Modeling for BGA in High-Speed Package

This paper discussed the package selection and BGA signal pin assignment consideration for high-end ASIC design with over 400 SerDes (Serializer Deserializer) pairs for >10Gbps backplane interface. The ASIC package is using advanced high-performance organic build-up (BU) materials like GX13, GZ41 and thinner core in the stack-up to help reduce the package loss and improve the signal transmission on the highspeed SerDes links. For return loss and insertion loss studies, the main objectives are to investigate the core thickness, BU material properties, and routing configurations impact on the differential signalling. The design suggestions are then made at each area for performance and cost optimization. For crosstalk studies, various pin-out patterns for transmit to transmit or receive to receive signals, and transmit to receive signals, have been designed and studied to investigate signal coupling and PCB escape routing requirements. Both frequency and time domain simulations are performed to compare the signal isolation performance. The most optimized pin-out is then selected to achieve the overall required system performance. Lastly, various package substrate samples with different BU materials, core thicknesses and crosstalk structures are manufactured to validate package design performance using probe station technique.

ASIC package design optimization for 10 Gbps and above backplane serdes links

High speed serial links usually have extremely tight requirement on the quality of the signal channels, in terms of insertion loss and return loss. Along with an end-to-end channel design, the transition from plated-through-hole (PTH) via to fan-out traces on printed circuit board (PCB) creates unavoidable impedance discontinuity, which greatly impacts the channel return loss performance. It is important to understand and model this discontinuity for optimization purpose. This paper discusses several approaches of improving the channel's properties, by optimizing the via-to-trace transition. Considering the impedance continuity at via to trace fan-out region, usually bigger anti-pad size (to reduce capacitive discontinuity) and larger return-path area (to reduce inductive discontinuity) are employed. In this paper, we inserted a short segment of fan-out-traces, named as “transition traces”, with slightly lower impedance than the system impedance; it significantly helps on improving the overall return loss performance, while being able to take care of the above-mentioned capacitive and inductive discontinuities very well. Besides, the impact of various parameters, including transition trace impedance, anti-pad sizes on different layers, is analyzed; and the optimum combination of these design parameters is suggested. Lastly, the manufactured test board is measured to verify the optimization method.

Kelvin Qiu

Papers

Characterization of PCB Dielectric Properties Using Two Striplines on the Same Board

Design and modeling for chip-to-chip communication at 20 Gbps

Analytical Equivalent Circuit Modeling for BGA in High-Speed Package

ASIC package design optimization for 10 Gbps and above backplane serdes links

PCB via to trace return loss optimization for >25Gbps serial links