K
Kento Kimura
Researcher at Tokyo Institute of Technology
Publications - 21
Citations - 515
Kento Kimura is an academic researcher from Tokyo Institute of Technology. The author has contributed to research in topics: Phase-locked loop & CMOS. The author has an hindex of 10, co-authored 21 publications receiving 358 citations.
Papers
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Journal ArticleDOI
64-QAM 60-GHz CMOS Transceivers for IEEE 802.11ad/ay
Rui Wu,Ryo Minami,Yuuki Tsukui,Seitaro Kawai,Yuuki Seo,Shinji Sato,Kento Kimura,Satoshi Kondo,Tomohiro Ueno,Nurul Fajri,Shoutarou Maki,Noriaki Nagashima,Yasuaki Takeuchi,Tatsuya Yamaguchi,Ahmed Eleojo Musa,Korkut Kaan Tokgoz,Teerachot Siriburanon,Bangan Liu,Yun Wang,Jian Pang,Ning Li,Masaya Miyahara,Kenichi Okada,Akira Matsuzawa +23 more
TL;DR: This paper presents 64-quadrature amplitude modulation (QAM) 60-GHz CMOS transceivers with four-channel bonding capability, which can be categorized into a one-stream transceiver and a two-stream frequency-interleaved (FI) transceiver.
Journal ArticleDOI
A Low-Power Low-Noise mm-Wave Subsampling PLL Using Dual-Step-Mixing ILFD and Tail-Coupling Quadrature Injection-Locked Oscillator for IEEE 802.11ad
Teerachot Siriburanon,Satoshi Kondo,Makihiko Katsuragi,Hanli Liu,Kento Kimura,Wei Deng,Kenichi Okada,Akira Matsuzawa +7 more
TL;DR: This paper presents a low-power low-noise 60 GHz frequency synthesizer using a 20 GHz subsampling phase-locked loop (SS-PLL) and a 60 GHz tail-coupling quadrature injection-locked oscillator (QILO) which results in a lower in-band phase noise and out-of- band phase noise, respectively.
Journal ArticleDOI
A Fractional- N Sub-Sampling PLL using a Pipelined Phase-Interpolator With an FoM of -250 dB
Aravind Tharayil Narayanan,Makihiko Katsuragi,Kento Kimura,Satoshi Kondo,Korkut Kaan Tokgoz,Kengo Nakata,Wei Deng,Kenichi Okada,Akira Matsuzawa +8 more
TL;DR: A fractional-N sub-sampling PLL architecture based on pipelined phase-interpolator and Digital-to-Time-Converter and DTC enables efficient design of the multi-phase generation mechanism required for the fractional operation.
Journal ArticleDOI
A 50.1-Gb/s 60-GHz CMOS Transceiver for IEEE 802.11ay With Calibration of LO Feedthrough and I/Q Imbalance
Jian Pang,Shotaro Maki,Seitarou Kawai,Noriaki Nagashima,Yuuki Seo,Masato Dome,Hisashi Kato,Makihiko Katsuragi,Kento Kimura,Satoshi Kondo,Yuki Terashima,Hanli Liu,Teerachot Siriburanon,Aravind Tharayil Narayanan,Nurul Fajri,Tohru Kaneko,Toru Yoshioka,Bangan Liu,Yun Wang,Rui Wu,Ning Li,Korkut Kaan Tokgoz,Masaya Miyahara,Atsushi Shirane,Kenichi Okada +24 more
TL;DR: This paper presents a 60-GHz CMOS transceiver targeting the IEEE 802.11ay standard with a calibration block for local oscillator feedthrough and I/Q imbalance featuring high accuracy and low power consumption integrated with the transceiver, capable of boosting the data rate with higher order modulation scheme and wider channel-bonding bandwidth.
Proceedings ArticleDOI
A 60-GHz sub-sampling frequency synthesizer using sub-harmonic injection-locked quadrature oscillators
Teerachot Siriburanon,Tomohiro Ueno,Kento Kimura,Satoshi Kondo,Wei Deng,Kenichi Okada,Akira Matsuzawa +6 more
TL;DR: This paper presents a 60-GHz sub-harmonic injection-locked quadrature frequency synthesizer with subsampling operation that allows the proposed synthesizer to achieve relatively lower in-band phase noise through the use of sub-sampling operation, as well as good out-of-bandphase noise throughThe proposed synthesizers has been implemented in a standard 65-nm CMOS technology.