Showing papers by "Keshab K. Parhi published in 2011"

Seizure prediction with spectral power of EEG using cost-sensitive support vector machines

Abstract: Summary Purpose: We propose a patient-specific algorithm for seizure prediction using multiple features of spectral power from electroencephalogram (EEG) and support vector machine (SVM) classification. Methods: The proposed patient-specific algorithm consists of preprocessing, feature extraction, SVM classification, and postprocessing. Preprocessing removes artifacts of intracranial EEG recordings and they are further preprocessed in bipolar and/or time-differential methods. Features of spectral power of raw, or bipolar and/or time-differential intracranial EEG (iEEG) recordings in nine bands are extracted from a sliding 20-s–long and half-overlapped window. Nine bands are selected based on standard EEG frequency bands, but the wide gamma bands are split into four. Cost-sensitive SVMs are used for classification of preictal and interictal samples, and double cross-validation is used to achieve in-sample optimization and out-of-sample testing. We postprocess SVM classification outputs using the Kalman Filter and it removes sporadic and isolated false alarms. The algorithm has been tested on iEEG of 18 patients of 20 available in the Freiburg EEG database who had three or more seizure events. To investigate the discriminability of the features between preictal and interictal, we use the Kernel Fisher Discriminant analysis. Key findings: The proposed patient-specific algorithm for seizure prediction has achieved high sensitivity of 97.5% with total 80 seizure events and a low false alarm rate of 0.27 per hour and total false prediction times of 13.0% over a total of 433.2 interictal hours by bipolar preprocessing (92.5% sensitivity, a false positive rate of 0.20 per hour, and false prediction times of 9.5% by time-differential preprocessing). This high prediction rate demonstrates that seizures can be predicted by the patient-specific approach using linear features of spectral power and nonlinear classifiers. Bipolar and/or time-differential preprocessing significantly improves sensitivity and specificity. Spectral powers in high gamma bands are the most discriminating features between preictal and interictal. Significance: High sensitivity and specificity are achieved by nonlinear classification of linear features of spectral power. Power changes in certain frequency bands already demonstrated their possibilities for seizure prediction indicators, but we have demonstrated that combining those spectral power features and classifying them in a multivariate approach led to much higher prediction rates. Employing only linear features is advantageous, especially when it comes to an implantable device, because they can be computed rapidly with low power consumption.

Reduced-Latency SC Polar Decoder Architectures

Abstract: Polar codes have become one of the most favorable capacity achieving error correction codes (ECC) along with their simple encoding method. However, among the very few prior successive cancellation (SC) polar decoder designs, the required long code length makes the decoding latency high. In this paper, conventional decoding algorithm is transformed with look-ahead techniques. This reduces the decoding latency by 50%. With pipelining and parallel processing schemes, a parallel SC polar decoder is proposed. Sub-structure sharing approach is employed to design the merged processing element (PE). Moreover, inspired by the real FFT architecture, this paper presents a novel input generating circuit (ICG) block that can generate additional input signals for merged PEs on-the-fly. Gate-level analysis has demonstrated that the proposed design shows advantages of 50% decoding latency and twice throughput over the conventional one with similar hardware cost.

High-Speed Parallel Architectures for Linear Feedback Shift Registers

Abstract: Linear feedback shift register (LFSR) is an important component of the cyclic redundancy check (CRC) operations and BCH encoders. The contribution of this paper is two fold. First, this paper presents a mathematical proof of existence of a linear transformation to transform LFSR circuits into equivalent state space formulations. This transformation achieves a full speed-up compared to the serial architecture at the cost of an increase in hardware overhead. This method applies to all generator polynomials used in CRC operations and BCH encoders. Second, a new formulation is proposed to modify the LFSR into the form of an infinite impulse response (IIR) filter. We propose a novel high speed parallel LFSR architecture based on parallel IIR filter design, pipelining and retiming algorithms. The advantage of the proposed approach over the previous architectures is that it has both feedforward and feedback paths. We further propose to apply combined parallel and pipelining techniques to eliminate the fanout effect in long generator polynomials. The proposed scheme can be applied to any generator polynomial, i.e., any LFSR in general. The proposed parallel architecture achieves better area-time product compared to the previous designs.

Synchronous sequential computation with molecular reactions

Abstract: Just as electronic systems implement computation in terms of voltage (energy per unit charge), molecular systems compute in terms of chemical concentrations (molecules per unit volume). Prior work has established mechanisms for implementing logical and arithmetic functions including addition, multiplication, exponentiation, and logarithms with molecular reactions. In this paper, we present a general methodology for implementing synchronous sequential computation. We generate a four-phase clock signal through robust, sustained chemical oscillations. We implement memory elements by transferring concentrations between molecular types in alternating phases of the clock. We illustrate our design methodology with examples: a binary counter as well as a four-point, two-parallel FFT. We validate our designs through ODE simulations of mass-action chemical kinetics. We are exploring DNA-based computation via strand displacement as a possible experimental chassis.

Reconfigurable architectures for silicon Physical Unclonable Functions

Abstract: Physical Unclonable Functions (PUFs) are novel circuit primitives which store secret keys in silicon circuits by exploiting uncontrollable randomness due to manufacturing process variations. Previous work has mainly focused on static challenge-response behaviors. However, it has already been shown that a reconfigurable architecture of PUF will not only enable PUFs to meet practical application needs, but also can improve the reliability and security of PUF-based authentication or identification systems. In this paper, we propose several novel structures for non-FPGA reconfigurable silicon PUFs, which do not need any special fabrication methods and can overcome the limitations and drawbacks of FPGA-based techniques. Their performances are quantified by the inter-chip variation, intra-chip variation and reconfigurability tests.

Binary counting with chemical reactions.

Abstract: This paper describes a scheme for implementing a binary counter with chemical reactions. The value of the counter is encoded by logical values of "0" and "1" that correspond to the absence and presence of specific molecular types, respectively. It is incremented when molecules of a trigger type are injected. Synchronization is achieved with reactions that produce a sustained three-phase oscillation. This oscillation plays a role analogous to a clock signal in digital electronics. Quantities are transferred between molecular types in different phases of the oscillation. Unlike all previous schemes for chemical computation, this scheme is dependent only on coarse rate categories for the reactions ("fast" and "slow"). Given such categories, the computation is exact and independent of the specific reaction rates. Although conceptual for the time being, the methodology has potential applications in domains of synthetic biology such as biochemical sensing and drug delivery. We are exploring DNA-based computation via strand displacement as a possible experimental chassis.

Architecture Optimizations for the RSA Public Key Cryptosystem: A Tutorial

Abstract: The Rivest Shamir Adleman (RSA) cryptosystem, named after its creators, is one of the most popular public key cryptosystems. The RSA cryptosystem has been utilized for e-commerce, various forms of authentication, and virtual private networks. The importance of high security and faster implementations paved the way for RSA crypto-accelerators, hardware implementations of the RSA algorithm. This work consists of describing various approaches to implementing RSA crypto-accelerators based on the “textbook” version of the RSA cryptosystem and comparing their area requirements. Many of the techniques described here have applications elsewhere such as in digital signal processing and error correcting codes. This paper presents the four fundamental architectures: the bit- serial squaring architecture, two bit-serial systolic array modular multiplication architectures, and the interleaved modular multiplication architecture.

Power Reduction in Frequency-Selective FIR Filters Under Voltage Overscaling

Abstract: Supply voltage overscaling (VOS) has been studied recently for the design of low power finite-impulse response (FIR) filters. The supply voltage is deliberately overscaled for saving power, which introduces errors due to timing violation. These VOS-incurred errors are then compensated by using an estimation-based noise reduction scheme, at the cost of minimal performance degradation while achieving significant power savings. In this paper, novel noise reduction unit (NRU) architectures are proposed to solve two challenging problems. First, we propose to use a separate reliable mechanism for detecting VOS-incurred errors, which frees the estimator from detecting VOS-incurred errors, and consequently enables use of folding techniques and filter adaptation. Second, we propose a novel noise reduction architecture for compensating errors in broadband frequency-selective filters, which show loose statistical dependency that leads to poor estimation in conventional designs. In addition, we recognize that the location of VOS-errors is the most destructive cause to NRU performance degradation, which has not been adequately dealt with in existing literatures. Our proposed architectures are based on smoothing filters, which require minimal hardware overhead while limiting the estimation degradation due to relative dense error distribution. Compared to previous work, the simulation results show that for narrow-band filters our proposed schemes can improve the noise reduction performance by 10-22 dB while achieving the same or better power savings, and for broadband filters the proposed schemes achieve 9-21 dB performance gain while achieving 10.33%-51.74% power savings.

Combining evidence from spectral and source-like features for person recognition from humming

Abstract: In this paper, hum of a person is used in voice biometric system. In addition, recently proposed feature set, i.e., Variable length Teager Energy Based Mel Frequency Cepstral Coefficients (VTMFCC), is found to capture perceptually meaningful source-like information from hum signal. For person recognition, MFCC gives EER of 13.14% and %ID of 64.96%. A reduction in equal error rate (EER) by 0.2% and improvement in identification rate by 7.3 % is achieved when a score-level fusion system is employed by combining evidence from MFCC (system) and VTMFCC (source-like features) than MFCC alone. Results are reported for various feature dimensions and population sizes.

Parallel pipelined systems for computing the fast fourier transform

Abstract: The present invention relates to the design and implementation of parallel pipelined circuits for the fast Fourier transform (FFT). In this invention, an efficient way of designing FFT circuits using folding transformation and register minimization techniques is proposed. Based on the proposed scheme, novel parallel-pipelined architectures for the computation of complex fast Fourier transform are derived. The proposed architecture takes advantage of under utilized hardware in the serial architecture to derive L-parallel architectures without increasing the hardware complexity by a factor of L. The proposed circuits process L consecutive samples from a single-channel signal in parallel. The operating frequency of the proposed architecture can be decreased which in turn reduces the power consumption. The proposed scheme is general and suitable for applications such as communications, biomedical monitoring systems, and high speed OFDM systems.

A low complexity seizure prediction algorithm

Abstract: A new low complexity seizure prediction algorithm is proposed. The algorithm achieves high sensitivity and low false positive rates in 10 out of 18 epileptic patients from the Freiburg database. Its primary achievement is two orders of magnitude computational complexity reduction. The reduced complexity makes an implantable medical device application realizable. In the subset of ten highly predictable patients average sensitivity is 96%, average specificity is 0.25 false positives per hour, and 13.5% of time is spent in false alarms. For all eighteen patients tested, the average sensitivity is 83%, the average specificity is 0.38 false positives per hour, and the amount of time spent in false alarms is 21.1%. This result may be compared with sensitivity of 97.5%, specificity of 0.27 false positives per hour, and 13% of time is spent in false alarms of prior results without complexity reduction.

Asynchronous computation with molecular reactions

Abstract: Mass-action kinetics of chemical reaction networks (CRNs) is powerful to describe computations through transfers of chemical concentrations Here we present methods for asynchronously implementing digital signal processing (DSP) operations such as filtering with CRNs We first review an implementation of DSP operations using molecular reactions based on a three-phase transfer scheme This is an example of a locally asynchronous, globally synchronous implementation We then present a fully asynchronous method that transfers signals based on absence of other signals We illustrate our methodology with the design of finite impulse response (FIR) filters The computation is exact and independent of specific reaction rates Although conceptual for the time being, the proposed methodology has potential applications in domains of synthetic biology such as biochemical sensing and drug delivery

Systems and methods for sparse error removal in communications systems

Abstract: A method for robust demodulation of the communications system in presence of sparse severe impulse noise is presented. In this invention, the application of impulse noise removal in orthogonal frequency domain multiplexing systems is investigated. The impulse noise causes catastrophic accuracy degradation at the output of the fast Fourier transform operations at the receiver. In this invention, an impulse noise identification scheme is proposed to determine the presence of the impulse noise. An impulse noise value search algorithm at known location based on the steepest descent method, an impulse noise location algorithm, and a novel iterative impulse error correction scheme are presented to remove the sparse error and demodulate the transmitted symbols accurately.

Secure Variable Data Rate Transmission

Abstract: A novel secure variable data rate (SVDR) transmission method is presented along with an architecture for implementing the SVDR transmission. This method reduces transmission overhead requirements by allowing both parties to maintain the initialization vector information locally rather than by obtaining it from the received packet. The only requirement this method places on the transmission is to maintain the sequence. This brief shows a 70% reduction in the overhead for transmitting this sequence information with a window size of 10 and seven priority levels.

Frequency domain symbol synchronization for OFDM systems

Abstract: In this paper, we propose a synchronization technique to reduce transmit power in order to develop an ultra low power transmitter. A sequence with digital power 0 dBW is used as the preamble at the transmitter. Compared with the traditional preamble specified in the IEEE 802.11 standards, the transmit power consumption is reduced by at least 24 dBW. However, a preamble with unit power cannot be easily detected in the time domain. Therefore, we propose a novel frequency domain symbol synchronization scheme to obtain the frame start. To our best knowledge, this is the first such published scheme that performs symbol synchronization in the frequency domain. In addition, the power consumption of this preamble is lower than other existing methods. Under an AWGN channel with a certain carrier frequency offset (CFO), the proposed method provides significant improvements compared with previously proposed methods. The proposed method provides at least 10 dB gain in extremely low SNR environment to achieve perfect timing synchronization in an AWGN channel. Furthermore, under frequency selective fading channels used in IEEE 802.16 standard with a certain CFO, the proposed algorithm performs always better than other previously proposed methods.

Low-Latency SC Decoder Architectures for Polar Codes

Abstract: Nowadays polar codes are becoming one of the most favorable capacity achieving error correction codes for their low encoding and decoding complexity. However, due to the large code length required by practical applications, the few existing successive cancellation (SC) decoder implementations still suffer from not only the high hardware cost but also the long decoding latency. This paper presents novel several approaches to design low-latency decoders for polar codes based on look-ahead techniques. Look-ahead techniques can be employed to reschedule the decoding process of polar decoder in numerous approaches. However, among those approaches, only well-arranged ones can achieve good performance in terms of both latency and hardware complexity. By revealing the recurrence property of SC decoding chart, the authors succeed in reducing the decoding latency by 50% with look-ahead techniques. With the help of VLSI-DSP design techniques such as pipelining, folding, unfolding, and parallel processing, methodologies for four different polar decoder architectures have been proposed to meet various application demands. Sub-structure sharing scheme has been adopted to design the merged processing element (PE) for further hardware reduction. In addition, systematic methods for construction refined pipelining decoder (2nd design) and the input generating circuits (ICG) block have been given. Detailed gate-level analysis has demonstrated that the proposed designs show latency advantages over conventional ones with similar hardware cost.

Efficient Network for Non-Binary QC-LDPC Decoder

Abstract: This paper presents approaches to develop efficient network for non-binary quasi-cyclic LDPC (QC-LDPC) decoders. By exploiting the intrinsic shifting and symmetry properties of the check matrices, significant reduction of memory size and routing complexity can be achieved. Two different efficient network architectures for Class-I and Class-II non-binary QC-LDPC decoders have been proposed, respectively. Comparison results have shown that for the code of the 64-ary (1260, 630) rate-0.5 Class-I code, the proposed scheme can save more than 70.6% hardware required by shuffle network than the state-of-the-art designs. The proposed decoder example for the 32-ary (992, 496) rate-0.5 Class-II code can achieve a 93.8% shuffle network reduction compared with the conventional ones. Meanwhile, based on the similarity of Class-I and Class-II codes, similar shuffle network is further developed to incorporate both classes of codes at a very low cost.