Atomic layer deposition (ALD) is gaining attention as a thin film deposition method, uniquely suitable for depositing uniform and conformal films on complex three-dimensional topographies. The deposition of a film of a given material by ALD relies on the successive, separated, and self-terminating gas–solid reactions of typically two gaseous reactants. Hundreds of ALD chemistries have been found for depositing a variety of materials during the past decades, mostly for inorganic materials but lately also for organic and inorganic–organic hybrid compounds. One factor that often dictates the properties of ALD films in actual applications is the crystallinity of the grown film: Is the material amorphous or, if it is crystalline, which phase(s) is (are) present. In this thematic review, we first describe the basics of ALD, summarize the two-reactant ALD processes to grow inorganic materials developed to-date, updating the information of an earlier review on ALD [R. L. Puurunen, J. Appl. Phys. 97, 121301 (2005)], and give an overview of the status of processing ternary compounds by ALD. We then proceed to analyze the published experimental data for information on the crystallinity and phase of inorganic materials deposited by ALD from different reactants at different temperatures. The data are collected for films in their as-deposited state and tabulated for easy reference. Case studies are presented to illustrate the effect of different process parameters on crystallinity for representative materials: aluminium oxide, zirconium oxide, zinc oxide, titanium nitride, zinc zulfide, and ruthenium. Finally, we discuss the general trends in the development of film crystallinity as function of ALD process parameters. The authors hope that this review will help newcomers to ALD to familiarize themselves with the complex world of crystalline ALD films and, at the same time, serve for the expert as a handbook-type reference source on ALD processes and film crystallinity.

Crystallinity of inorganic films grown by atomic layer deposition: Overview and general trends

Nonvolatile RAM using resistance contrast in phase-change materials [or phase-change RAM (PCRAM)] is a promising technology for future storage-class memory. However, such a technology can succeed only if it can scale smaller in size, given the increasingly tiny memory cells that are projected for future technology nodes (i.e., generations). We first discuss the critical aspects that may affect the scaling of PCRAM, including materials properties, power consumption during programming and read operations, thermal cross-talk between memory cells, and failure mechanisms. We then discuss experiments that directly address the scaling properties of the phase-change materials themselves, including studies of phase transitions in both nanoparticles and ultrathin films as a function of particle size and film thickness. This work in materials directly motivated the successful creation of a series of prototype PCRAM devices, which have been fabricated and tested at phase-change material cross-sections with extremely small dimensions as low as 3 nm × 20 nm. These device measurements provide a clear demonstration of the excellent scaling potential offered by this technology, and they are also consistent with the scaling behavior predicted by extensive device simulations. Finally, we discuss issues of device integration and cell design, manufacturability, and reliability.

Phase-change random access memory: a scalable technology

The authors survey the current state of phase change memory (PCM), a nonvolatile solid-state memory technology built around the large electrical contrast between the highly resistive amorphous and highly conductive crystalline states in so-called phase change materials. PCM technology has made rapid progress in a short time, having passed older technologies in terms of both sophisticated demonstrations of scaling to small device dimensions, as well as integrated large-array demonstrators with impressive retention, endurance, performance, and yield characteristics. They introduce the physics behind PCM technology, assess how its characteristics match up with various potential applications across the memory-storage hierarchy, and discuss its strengths including scalability and rapid switching speed. Challenges for the technology are addressed, including the design of PCM cells for low reset current, the need to control device-to-device variability, and undesirable changes in the phase change material that c...

Phase change memory technology

This review paper explores considerations for ultimate CMOS transistor scaling Transistor architectures such as extremely thin silicon-on-insulator and FinFET (and related architectures such as TriGate, Omega-FET, Pi-Gate), as well as nanowire device architectures, are compared and contrasted Key technology challenges (such as advanced gate stacks, mobility, resistance, and capacitance) shared by all of the architectures will be discussed in relation to recent research results

Considerations for Ultimate CMOS Scaling

Atomic layer etching (ALE) is a technique for removing thin layers of material using sequential reaction steps that are self-limiting. ALE has been studied in the laboratory for more than 25 years. Today, it is being driven by the semiconductor industry as an alternative to continuous etching and is viewed as an essential counterpart to atomic layer deposition. As we enter the era of atomic-scale dimensions, there is need to unify the ALE field through increased effectiveness of collaboration between academia and industry, and to help enable the transition from lab to fab. With this in mind, this article provides defining criteria for ALE, along with clarification of some of the terminology and assumptions of this field. To increase understanding of the process, the mechanistic understanding is described for the silicon ALE case study, including the advantages of plasma-assisted processing. A historical overview spanning more than 25 years is provided for silicon, as well as ALE studies on oxides, III–V compounds, and other materials. Together, these processes encompass a variety of implementations, all following the same ALE principles. While the focus is on directional etching, isotropic ALE is also included. As part of this review, the authors also address the role of power pulsing as a predecessor to ALE and examine the outlook of ALE in the manufacturing of advanced semiconductor devices.

https://avs.scitation.org/doi/pdf/10.1116/1.4913379

Overview of atomic layer etching in the semiconductor industry

A multiple gate semiconductor device. The device includes at least two gates. The dopant distribution in the semiconductor body of the device varies from a low value near the surface of the body towards a higher value inside the body of the device.

Multiple gate semiconductor device and method for forming same

In this paper, we compare the performances of FinFETs, lateral gate-all-around (GAA) FETs, and vertical GAAFETs (VFETs) at 7-nm node dimensions and beyond Comparison is done at ring oscillator level accounting not only for front-end of line devices but also for interconnects It is demonstrated that FinFETs fail to maintain the performance at scaled dimensions, while VFETs demonstrate good scalability and eventually outperform lateral devices both in speed and power consumption Lateral GAAFETs show better scalability with respect to FinFETs but still consume 35% more energy per switch than VFETs if made under 5-nm node design rules

Vertical GAAFETs for the Ultimate CMOS Scaling

A CMOS circuit for and method of forming a FinFET device is disclosed. The method includes providing a substrate comprising a semiconductor layer, forming on the semiconductor layer active areas insulated from each other by field areas, forming at least one dummy gate on at least one of said active areas and forming source and drain regions on the at least one of the active areas. The method also includes covering the substrate with an insulating layer leaving said dummy gate exposed and forming an open cavity by patterning the dummy gate to form a dummy fin and a semiconductor fin aligned to said dummy fin, both fins extending from the source to the drain regions.

Integrated semiconductor fin device and a method for manufacturing such device

A commercial technology computer-aided design device simulator was extended to allow electrical simulations of sub-100-nm germanium pMOSFETs. Parameters for generation/recombination mechanisms (Shockley-Read-Hall, trap-assisted tunneling, and band-to-band tunneling) and mobility models (impurity scattering and mobility reduction at high lateral and transversal field) are provided. The simulations were found to correspond well with the experimental I- V data on our Ge transistors at gate lengths down to 70 nm and various bias conditions. The effect of changes in halo dose and extension energies is discussed, illustrating that the set of models presented in this paper can prove useful to optimize and predict the performance of new Ge-based devices.

Electrical TCAD Simulations of a Germanium pMOSFET Technology

Through-silicon via (TSV) constitutes a key component interconnecting adjacent dies vertically to form 3-D integrated circuits. In this letter, we propose a method to exploit the TSV C-V behavior in a p-silicon substrate to achieve minimum TSV capacitance during 3-D circuit operation. The nature of the TSV C-V characteristics depends both on TSV architecture and TSV manufacturing process, and both these factors should be optimized to obtain the minimum depletion capacitance in the desired operating voltage region. Measured C-V characteristics of the TSV demonstrate the effectiveness of the method.

Kristin De Meyer

Papers

Multiple gate semiconductor device and method for forming same

Vertical GAAFETs for the Ultimate CMOS Scaling

Integrated semiconductor fin device and a method for manufacturing such device

Electrical TCAD Simulations of a Germanium pMOSFET Technology

Through-Silicon-Via Capacitance Reduction Technique to Benefit 3-D IC Performance