K
Ku-Feng Lin
Researcher at TSMC
Publications - 34
Citations - 890
Ku-Feng Lin is an academic researcher from TSMC. The author has contributed to research in topics: Transistor & Sense amplifier. The author has an hindex of 12, co-authored 34 publications receiving 809 citations. Previous affiliations of Ku-Feng Lin include Industrial Technology Research Institute & National Tsing Hua University.
Papers
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Proceedings ArticleDOI
A 4Mb embedded SLC resistive-RAM macro with 7.2ns read-write random-access time and 160ns MLC-access capability
Shyh-Shyuan Sheu,Meng-Fan Chang,Ku-Feng Lin,Che-Wei Wu,Yu-Sheng Chen,Pi-Feng Chiu,Chia-Chen Kuo,Yih-Shan Yang,Pei-Chia Chiang,Wen-Pin Lin,Che-He Lin,Heng-Yuan Lee,Pei-Yi Gu,Sum-Min Wang,Frederick T. Chen,Keng-Li Su,Chen-Hsin Lien,Kuo-Hsing Cheng,Hsin-Tun Wu,Tzu-Kun Ku,Ming-Jer Kao,Ming-Jinn Tsai +21 more
TL;DR: This work proposes process/resistance variation-insensitive read schemes for embedded RRAM to achieve fast read speeds with high yields and an embedded mega-bit scale, single-level-cell (SLC) RRAM macro with sub-8ns read-write random-access time is presented.
Proceedings ArticleDOI
19.4 embedded 1Mb ReRAM in 28nm CMOS with 0.27-to-1V read using swing-sample-and-couple sense amplifier and self-boost-write-termination scheme
Meng-Fan Chang,Jui-Jen Wu,Tun-Fei Chien,Yen-Chen Liu,Ting-Chin Yang,Wen-Chao Shen,Ya-Chin King,Chorng-Jung Lin,Ku-Feng Lin,Yu-Der Chih,Sreedhar Natarajan,Jonathan Chang +11 more
TL;DR: This study develops a swing-sample-andcouple (SSC) voltage-mode sense amplifier (VSA) to overcome (1), enabling 1.8× greater SM for lower RD-VDDMIN and 1.7× faster T-sub>AC across various V, compared to conventional differential-input (CD) VSAs.
Proceedings ArticleDOI
A low store energy, low VDDmin, nonvolatile 8T2R SRAM with 3D stacked RRAM devices for low power mobile applications
Pi-Feng Chiu,Meng-Fan Chang,Shyh-Shyuan Sheu,Ku-Feng Lin,Pei-Chia Chiang,Che-Wei Wu,Wen-Pin Lin,Chih-He Lin,Ching-Chih Hsu,Frederick T. Chen,Keng-Li Su,Ming-Jer Kao,Ming-Jinn Tsai +12 more
TL;DR: This work demonstrates the first fabricated macro-level RRAM-based nonvolatile SRAM (nvSRAM) that use a new 8T2R (Rnv8T) cell to achieve fast NVM storage and low VDDmin read/write operations.
Journal ArticleDOI
A High-Speed 7.2-ns Read-Write Random Access 4-Mb Embedded Resistive RAM (ReRAM) Macro Using Process-Variation-Tolerant Current-Mode Read Schemes
Meng-Fan Chang,Shyh-Shyuan Sheu,Ku-Feng Lin,Che-Wei Wu,Chia-Chen Kuo,Pi-Feng Chiu,Yih-Shan Yang,Yu-Sheng Chen,Heng-Yuan Lee,Chen-Hsin Lien,Frederick T. Chen,Keng-Li Su,Tzu-Kun Ku,Ming-Jer Kao,Ming-Jinn Tsai +14 more
TL;DR: This study fabricated a 4-Mb ReRAM macro to confirm the effectiveness of the proposed schemes for both SLC and MLC operations and proposes two process-variation-tolerant schemes for current-mode read operation of ReRAM: parallel-series reference-cell (PSRC) and process-temperature-aware dynamic BL-bias (PTADB) schemes.
Proceedings ArticleDOI
A 0.5V 4Mb logic-process compatible embedded resistive RAM (ReRAM) in 65nm CMOS using low-voltage current-mode sensing scheme with 45ns random read time
Meng-Fan Chang,Che-Wei Wu,Chia-Cheng Kuo,Shin-Jang Shen,Ku-Feng Lin,Shu-Meng Yang,Ya-Chin King,Chorng-Jung Lin,Yu-Der Chih +8 more
TL;DR: A body-drain-driven CSA (BDD-CSA) with dynamic BL bias voltage (VBL) and small VHR for larger sensing margins is developed to achieve a lower VDDmin, faster read speed, and better tolerance of read cell current (ICELL) and BL leakage current (IBL-LEAK) variations compared to conventional CSAs.