M
Meng-Fan Chang
Researcher at National Tsing Hua University
Publications - 317
Citations - 8873
Meng-Fan Chang is an academic researcher from National Tsing Hua University. The author has contributed to research in topics: Static random-access memory & Resistive random-access memory. The author has an hindex of 41, co-authored 281 publications receiving 5538 citations. Previous affiliations of Meng-Fan Chang include TSMC & Tsinghua University.
Papers
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Journal ArticleDOI
Neuro-inspired computing chips
Wenqiang Zhang,Bin Gao,Jianshi Tang,Peng Yao,Shimeng Yu,Meng-Fan Chang,Hoi-Jun Yoo,He Qian,Huaqiang Wu +8 more
TL;DR: The development of neuro-inspired computing chips and their key benchmarking metrics are reviewed, providing a co-design tool chain and proposing a roadmap for future large-scale chips are provided and a future electronic design automation tool chain is proposed.
Journal ArticleDOI
Small-Subthreshold-Swing and Low-Voltage Flexible Organic Thin-Film Transistors Which Use HfLaO as the Gate Dielectric
TL;DR: Pentacene organic thin-film transistors (OTFTs) with a high-kappa HfLaO dielectric were integrated onto flexible polyimide substrates as discussed by the authors.
Proceedings ArticleDOI
A 4Mb embedded SLC resistive-RAM macro with 7.2ns read-write random-access time and 160ns MLC-access capability
Shyh-Shyuan Sheu,Meng-Fan Chang,Ku-Feng Lin,Che-Wei Wu,Yu-Sheng Chen,Pi-Feng Chiu,Chia-Chen Kuo,Yih-Shan Yang,Pei-Chia Chiang,Wen-Pin Lin,Che-He Lin,Heng-Yuan Lee,Pei-Yi Gu,Sum-Min Wang,Frederick T. Chen,Keng-Li Su,Chen-Hsin Lien,Kuo-Hsing Cheng,Hsin-Tun Wu,Tzu-Kun Ku,Ming-Jer Kao,Ming-Jinn Tsai +21 more
TL;DR: This work proposes process/resistance variation-insensitive read schemes for embedded RRAM to achieve fast read speeds with high yields and an embedded mega-bit scale, single-level-cell (SLC) RRAM macro with sub-8ns read-write random-access time is presented.
Proceedings ArticleDOI
24.1 A 1Mb Multibit ReRAM Computing-In-Memory Macro with 14.6ns Parallel MAC Computing Time for CNN Based AI Edge Processors
Cheng-Xin Xue,Wei-Hao Chen,Je-Syu Liu,Jiafang Li,Wei-Yu Lin,Wei-En Lin,Jing-Hong Wang,Wei-Chen Wei,Ting-Wei Chang,Tung-Cheng Chang,Tsung-Yuan Huang,Hui-Yao Kao,Shih-Ying Wei,Yen-Cheng Chiu,Chun-Ying Lee,Chung-Chuan Lo,Ya-Chin King,Chorng-Jung Lin,Ren-Shuo Liu,Chih-Cheng Hsieh,Kea-Tiong Tang,Meng-Fan Chang +21 more
TL;DR: This work proposes a serial-input non-weighted product (SINWP) structure to optimize the tradeoff between area, tMAC and EMAC, and a down-scaling weighted current translator and positive-negative current- subtractor (PN-ISUB) for short delay, a small offset and a compact read-path area.
Proceedings ArticleDOI
A 65nm 1Mb nonvolatile computing-in-memory ReRAM macro with sub-16ns multiply-and-accumulate for binary DNN AI edge processors
Wei-Hao Chen,K. C. Li,Wei-Yu Lin,K. C. Hsu,Pin-Yi Li,Cheng-Han Yang,Cheng-Xin Xue,En-Yu Yang,Yen-Kai Chen,Yun-Sheng Chang,Tzu-Hsiang Hsu,Ya-Chin King,Chorng-Jung Lin,Ren-Shuo Liu,Chih-Cheng Hsieh,Kea-Tiong Tang,Meng-Fan Chang +16 more
TL;DR: Many artificial intelligence (AI) edge devices use nonvolatile memory (NVM) to store the weights for the neural network (trained off-line on an AI server), and require low-energy and fast I/O accesses.