K
Kyndylan Nienhuis
Researcher at University of Cambridge
Publications - 8
Citations - 368
Kyndylan Nienhuis is an academic researcher from University of Cambridge. The author has contributed to research in topics: Semantics (computer science) & Concurrency. The author has an hindex of 6, co-authored 8 publications receiving 287 citations.
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Book ChapterDOI
The Problem of Programming Language Concurrency Semantics
TL;DR: This paper argues that the Java Memory Model has been shown to be unsound with respect to standard compiler optimisations, while the C/C++11 model is too weak, admitting undesirable thin-air executions.
Proceedings ArticleDOI
Into the depths of C: elaborating the de facto standards
Kayvan Memarian,Justus Matthiesen,James Lingard,Kyndylan Nienhuis,David Chisnall,Robert N. M. Watson,Peter Sewell +6 more
TL;DR: An in-depth analysis of the design space for the semantics of pointers and memory in C as it is used in practice is described, a step towards clear, consistent, and accepted semantics for the various use-cases of C.
Capability Hardware Enhanced RISC Instructions: CHERI Instruction-Set Architecture (Version 7)
Robert N. M. Watson,Peter G. Neumann,Jonathan Woodruff,Michael Roe,Hesham Almatary,Jonathan Anderson,John Baldwin,David Chisnall,Brooks Davis,Nathaniel Wesley Filardo,Alexandre Joannou,Ben Laurie,A. Theodore Markettos,Simon W. Moore,Steven J. Murdoch,Kyndylan Nienhuis,Robert M. Norton,Alexander Richardson,Peter Rugg,Peter Sewell,Stacey Son,Hongyan Xia +21 more
TL;DR: This document describes the rapidly maturing design for the Capability Hardware Enhanced RISC Instructions (CHERI) Instruction-Set Architecture (ISA), and provides reference documentation for the CHERI instruction-set architecture and potential memory models, along with their requirements.
Proceedings ArticleDOI
An operational semantics for C/C++11 concurrency
TL;DR: This work develops an operational model for C/C++11 concurrency that covers all the features of the previous formalised axiomatic model, and has a mechanised proof that the two are equivalent, in Isabelle/HOL.
Proceedings ArticleDOI
Mixed-size concurrency: ARM, POWER, C/C++11, and SC
Shaked Flur,Susmit Sarkar,Christopher Pulte,Kyndylan Nienhuis,Luc Maranget,Kathryn E. Gray,Ali Sezgin,Mark Batty,Peter Sewell +8 more
TL;DR: It is shown that adding a memory barrier between each instruction does not restore sequential consistency, and the C/C++11 model is extended to support non-atomic mixed-size memory accesses, a necessary step towards semantics for real-world shared-memory concurrent code, beyond litmus tests.