Kyoung-Ho Kim

TL;DR: In this paper, a circuit and method for controlling the gate voltage of a transistor acting between local and global input/output lines of a memory device is presented, where the output node disposed for receiving a signal indicative of an input or output operation, and the gate node in signal communication with a gate of the local from/to global input multiplexer for providing a gate signal of a first or second level in the presence of the output operation.

TL;DR: The proposed DBI circuit uses an analog majority voter insensitive to mismatch for small area and delay, and a dual duty cycle corrector (DCC) is used to reduce duty error and jitter by averaging two outputs of two DCCs.

TL;DR: This work tackles challenges in GDDR5 such as clock jitter and signal integrity with respect to forwarded clocking, data training for write and read de-skewing, clock training, channel-error detection, bank group and data coding.

TL;DR: In this paper, a latency control circuit and method of auto-precharge control and method thereof are provided. But they do not specify a precharging operation with the auto precharge control circuit.

TL;DR: In this article, the authors propose an apparatus for aligning input data in a semiconductor device, which includes at least one alignment block and a decision block, for serial input data into groups of parallel data synchronized to a divided data strobe signal for increasing margin between the maximum and minimum tDQSS values.