The CMOS technology area has quickly grown, calling for a new text--and here it is, covering the analysis and design of CMOS integrated circuits that practicing engineers need to master to succeed. Filled with many examples and chapter-ending problems, the book not only describes the thought process behind each circuit topology, but also considers the rationale behind each modification. The analysis and design techniques focus on CMOS circuits but also apply to other IC technologies.
Table of contents

1 Introduction to Analog Design
2 Basic MOS Device Physics
3 Single-Stage Amplifiers
4 Differential Amplifiers
5 Passive and Active Current Mirrors
6 Frequency Response of Amplifiers
7 Noise
8 Feedback
9 Operational Amplifiers
10 Stability and Frequency Compensation
11 Bandgap References
12 Introduction to Switched-Capacitor Circuits
13 Nonlinearity and Mismatch
14 Oscillators
15 Phase-Locked Loops
16 Short-Channel Effects and Device Models
17 CMOS Processing Technology
18 Layout and Packaging

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Design of Analog CMOS Integrated Circuits

Single-crystal silicon is being increasingly employed in a variety of new commercial products not because of its well-established electronic properties, but rather because of its excellent mechanical properties. In addition, recent trends in the engineering literature indicate a growing interest in the use of silicon as a mechanical material with the ultimate goal of developing a broad range of inexpensive, batch-fabricated, high-performance sensors and transducers which are easily interfaced with the rapidly proliferating microprocessor. This review describes the advantages of employing silicon as a mechanical material, the relevant mechanical characteristics of silicon, and the processing techniques which are specific to micromechanical structures. Finally, the potentials of this new technology are illustrated by numerous detailed examples from the literature. It is clear that silicon will continue to be aggressively exploited in a wide variety of mechanical applications complementary to its traditional role as an electronic material. Furthermore, these multidisciplinary uses of silicon will significantly alter the way we think about all types of miniature mechanical devices and components.

Silicon as a mechanical material

An analytical model for the above-threshold characteristics of long-channel, small-grain and thin channel polysilicon thin film transistors (TFT's) is presented. This model is constructed by considering the barrier potential and the carrier trapping effect at grain boundaries of the channel. A band tail state located at E/sub c/-0.15 eV is taken into account to simulate the I-V characteristics. Based on the model, the theoretically simulated results show good agreement with experimental data of plasma-passivated and unpassivated TFT devices in a wide range of gate and drain biases and temperature. The correlation of transconductance to gate bias is also investigated. It is found that the decrease of grain-boundary barrier potential with gate voltage enhances the transconductance, while this enhancement effect becomes insignificant and causes a decrease of transconductance at high gate bias. >

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An analytical model for the above-threshold characteristics of polysilicon thin-film transistors

The basic principles of using sonographic techniques for imaging the elastic properties of tissues are described, with particular emphasis on elastography. After some preliminaries that describe some basic tissue stiffness measurements and some contrast transfer limitations of strain images are presented, four types of elastograms are described, which include axial strain, lateral strain, modulus and Poisson's ratio elastograms. The strain filter formalism and its utility in understanding the noise performance of the elastographic process is then given, as well as its use for various image improvements. After discussing some main classes of elastographic artefacts, the paper concludes with recent results of tissue elastography in vitro and in vivo.

Elastography: ultrasonic estimation and imaging of the elastic properties of tissues.

The processing parameters of monolithic polycrystalline silicon resistors are examined, and the effect of grain size on the sensitivity of polysilicon resistivity versus doping concentration is studied theoretically and experimentally. Because existing models for polysilicon do not accurately predict resistivity dependence on doping concentration as grain size increases above 600 A, a modified trapping model for polysilicon with different grain sizes and under various applied biases is introduced. Good agreement between theory and experiments demonstrates that an increase in grain size from 230 to 1220 A drastically reduces the sensitivity of polysilicon resistivity to doping levels by two orders of magnitude. Such an increase is achieved by modifications of the integrated-circuit processes. Design criteria for the optimization of monolithic polysilicon resistors have also been established based on resistivity control, thermal properties, and device geometry.

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Modeling and optimization of monolithic polycrystalline silicon resistors

0.4‐μm‐thick polycrystalline silicon deposited in a low‐pressure CVD reactor was implanted with B to a dose of 5×1014/cm2 and then irradiated in a cw laser scanning apparatus. The laser annealing produced an increase in grain size from ∼500 A to long narrow crystals of the order of ∼25×2 μ, as observed by TEM. Each grain was found to be defect free and extended all the way to the underlying Si3N4. Electrical measurements show 100% doping activity with a Hall mobility of about 45 cm2/V sec, which is close to single‐crystal mobility at the same carrier concentration. Thermal annealing produces material with an average grain size of 1000 A and a resistivity higher by a factor of 2.2 than that obtained with the laser anneal. Laser annealing performed after a thermal anneal reduces the resistivity to approximately the same value obtained by laser annealing only.

cw laser anneal of polycrystalline silicon: Crystalline structure, electrical properties

Anisotropic etching of silicon with the hydrazine‐water mixture is studied and characterized for its practical use in integrated circuit technology. The solution is applied to {100} wafers where the etch presents a v‐shaped cross section limited at the side‐walls by {111} planes and at the bottom by a {100} plane. The etching process is evaluated in terms of the etch rate of the {100} plane, quality of side‐walls and bottom surface, and corner rounding. It is shown that the results are both concentration and temperature dependent. The optimal temperature for the etching process is found to be 100°C for both simple temperature control and high quality etching. It is also shown that the optimal mixture concentration must be choesn according to the particular use of the anisotropic etching. The optimal volume concentrations of hydrazine for the various applications are: 65% for VMOS devices and for v‐groove isolation rings, 70–80% for two‐level structures with flat bottom surface, and for electrode and sensor fabrication.

Optimization of the Hydrazine‐Water Solution for Anisotropic Etching of Silicon in Integrated Circuit Technology

A quantitative trapping model is introduced to describe the electrical properties of a semiconductor-grain-boundary-semiconductor (SGBS) barrier in polysilicon films over a wide temperature range. The grain-boundary scattering effects on carrier transport are studied analytically by examining the behavior of the height and width of a rectangular grain-boundary potential barrier. The model also verifies the applicability of a single-crystal band diagram for the crystallite within which an impurity level exists. Carder transport includes not only thermionic field emission through the space-charge potential barrier resulting from trapping effects and through the grain-boundary scattering potential barrier but also thermionic emission over these barriers. Thermionic emission dominates at high temperatures; however, at low temperatures, thermionic field emission becomes more important and the grain-boundary scattering effects are an essential factor. By characterizing the experimental data of the I-V characteristics, resistivity, mobility, and carrier concentration, this model enhances the understanding of the current transport in polysilicon films with grain sizes from 100 A to 1 µm, doping levels from 1 × 1016to 8 × 1019cm-3, and measurement temperatures from -176 to 144°C. The limitations of the model are also discussed.

https://ir.nctu.edu.tw:443/bitstream/11536/4903/1/A1983QG04400010.pdf

A conduction model for semiconductor-grain-boundary-semiconductor barriers in polycrystalline-silicon films

Low resistance, doped polycrystalline semiconductor connection patterns are fabricated by scanning a doped polycrystalline layer with a laser beam thereby increasing the crystal grain size, reducing defects in the grains, increasing charge carrier mobility and as a result reducing material resistivity. Semiconductor devices having increased circuit density and speed are realized through use of laser annealed polycrystalline semiconductor resistors, contacts and interconnections.

Levy Gerzberg

Papers

Modeling and optimization of monolithic polycrystalline silicon resistors

cw laser anneal of polycrystalline silicon: Crystalline structure, electrical properties

Optimization of the Hydrazine‐Water Solution for Anisotropic Etching of Silicon in Integrated Circuit Technology

A conduction model for semiconductor-grain-boundary-semiconductor barriers in polycrystalline-silicon films

Method of forming polycrystalline semiconductor interconnections, resistors and contacts by applying radiation beam