A software-defined radio receiver is designed from a low-power ADC perspective, exploiting programmability of windowed integration sampler and clock-programmable discrete-time analog filters. To cover the major frequency bands in use today, a wideband RF front-end, including the low-noise amplifier (LNA) and a wide tuning-range synthesizer, spanning over 800 MHz to 6 GHz is designed. The wideband LNA provides 18-20 dB of maximum gain and 3-3.5 dB of noise figure over 800 MHz to 6 GHz. A low 1/f noise and high-linearity mixer is designed which utilizes the passive mixer core properties and provides around +70 dBm IIP2 over the bandwidth of operation. The entire receiver circuits are implemented in 90-nm CMOS technology. Programmability of the receiver is tested for GSM and 802.11g standards

An 800-MHz–6-GHz Software-Defined Wireless Receiver in 90-nm CMOS

A software-defined radio (SDR) receiver with baseband programmable RF bandpass filter (BPF) and complex impedance match is presented. The passive mixer-first architecture used here allows the impedance characteristics of the receiver's baseband circuits to be translated to the RF port of the receiver. Tuning the resistance at the baseband port allows for a real impedance match to the antenna. The addition of "complex feedback" between I and Q paths allows for matching to the imaginary component of the antenna impedance. By implementing both real and imaginary components with resistors in feedback around low noise baseband amplifiers, noise figure is also kept low. Tunable sampling capacitors on the baseband side of the passive mixer translate to tunable-Q filters on the RF port which allow for very good out-of-band linearity. Furthermore, the concept of in-band and out-of-band must be redefined as the impedance match and BPF center frequency move with the LO frequency, such that matching and filtering track the receive frequency. Additionally, 8-phase mixing is shown to provide significant benefits such as impedance matching range, rejection of blockers at LO harmonics, and lower noise figure (NF). Measurements from the receiver implemented in 65 nm CMOS show 70 dB of gain, NF as low as 3 dB, and 25 dBm out-of-band IIP3. Furthermore, tunable impedance matching shows that S11 <;- 30 dB can be achieved at any receive frequency from 0.1-1.3 GHz.

A Passive Mixer-First Receiver With Digitally Controlled and Widely Tunable RF Interface

A new wideband receiver architecture is proposed that employs two separate passive-mixer-based downconversion paths, which enables noise cancelling, but avoids voltage gain at blocker frequencies. This approach significantly relaxes the trade-off between noise, out-of-band linearity and wideband operation. The resulting prototype in 40 nm is functional from 80 MHz to 2.7 GHz and achieves a 2 dB noise figure, which only degrades to 4.1 dB in the presence of a 0 dBm blocker.

A Blocker-Tolerant, Noise-Cancelling Receiver Suitable for Wideband Wireless Applications

A software-defined radio (SDR) receiver with improved robustness to out-of-band interference (OBI) is presented. Two main challenges are identified for an OBI-robust SDR receiver: out-of-band nonlinearity and harmonic mixing. Voltage gain at RF is avoided, and instead realized at baseband in combination with low-pass filtering to mitigate blockers and improve out-of-band IIP3. Two alternative ?iterative? harmonic-rejection (HR) techniques are presented to achieve high HR robust to mismatch: a) an analog two-stage polyphase HR concept, which enhances the HR to more than 60 dB; b) a digital adaptive interference cancelling (AIC) technique, which can suppress one dominating harmonic by at least 80 dB. An accurate multiphase clock generator is presented for a mismatch-robust HR. A proof-of-concept receiver is implemented in 65 nm CMOS. Measurements show 34 dB gain, 4 dB NF, and + 3.5 dBm in-band IIP3 while the out-of-band IIP3 is +16 dBm without fine tuning. The measured RF bandwidth is up to 6 GHz and the 8-phase LO works up to 0.9 GHz (master clock up to 7.2 GHz). At 0.8 GHz LO, the analog two-stage polyphase HR achieves a second to sixth order HR > 60 dB over 40 chips, while the digital AIC technique achieves HR > 80 dB for the dominating harmonic. The total power consumption is 50 mA from a 1.2 V supply.

/pdf/digitally-enhanced-software-defined-radio-receiver-robust-to-ictnclarjx.pdf

Digitally Enhanced Software-Defined Radio Receiver Robust to Out-of-Band Interference

The vision of embedding connectivity into billions of everyday objects runs into the reality of existing communication technologies -- there is no existing wireless technology that can provide reliable and long-range communication at tens of microwatts of power as well as cost less than a dime While backscatter is low-power and low-cost, it is known to be limited to short ranges This paper overturns this conventional wisdom about backscatter and presents the first wide-area backscatter system Our design can successfully backscatter from any location between an RF source and receiver, separated by 475 m, while being compatible with commodity LoRa hardware Further, when our backscatter device is co-located with the RF source, the receiver can be as far as 28 km away We deploy our system in a 4,800 ft2 (446 m2) house spread across three floors, a 13,024 ft2 (1210 m2) office area covering 41 rooms, as well as a one-acre (4046 m2) vegetable farm and show that we can achieve reliable coverage, using only a single RF source and receiver We also build a contact lens prototype as well as a flexible epidermal patch device attached to the human skin We show that these devices can reliably backscatter data across a 3,328 ft2 (309 m2) room Finally, we present a design sketch of a LoRa backscatter IC that shows that it costs less than a dime at scale and consumes only 925 mW of power, which is more than 1000x lower power than LoRa radio chipsets

https://dl.acm.org/doi/pdf/10.1145/3130970

LoRa Backscatter: Enabling The Vision of Ubiquitous Connectivity

A highly integrated 175-GHz 035-/spl mu/m CMOS transmitter is described The I/Q modulator-based transmitter facilitates integration through the use of a unique mixer, termed a harmonic-rejection mixer, and a wide loop bandwidth phase-locked loop (PLL) for the RF synthesizer The harmonic-rejection mixers are used to eliminate the need for a discrete IF filter and the use of a wide loop bandwidth PLL allowed for the complete integration of the synthesizers using low-Q components while achieving low phase noise The entire transmit signal path from the digital-to-analog converters to the power amplifier, including two fully integrated frequency synthesizers, is integrated into a single-chip solution The transmitter was tested with a testing buffer before the power amplifier (PA) and achieved less than 13/spl deg/ rms phase error when modulating a DCS-1800 GMSK signal The prototype consumed 151 mA from a 3-V supply A class-C PA, capable of driving 25 dBm off-chip, was included and the output was compared to the testing buffer with little change in the transmitter performance

A 1.75 GHz highly-integrated narrow-band CMOS transmitter with harmonic-rejection mixers

A fully integrated CMOS direct-conversion 5-GHz transceiver with automatic frequency control is implemented in a 0.18-/spl mu/m digital CMOS process and housed in an LPCC-48 package. This chip, along with a companion baseband chip, provides a complete 802.11a solution The transceiver consumes 150 mW in receive mode and 380 mW in transmit mode while transmitting +15-dBm output power. The receiver achieves a sensitivity of better than -93.7dBm and -73.9dBm for 6 Mb/s and 54 Mb/s, respectively (even using hard-decision decoding). The transceiver achieves a 4-dB receive noise figure and a +23-dBm transmitter saturated output power. The transmitter also achieves a transmit error vector magnitude of -33 dB. The IC occupies a total die area of 11.7 mm/sup 2/ and is packaged in a 48-pin LPCC package. The chip passes better than /spl plusmn/2.5-kV ESD performance. Various integrated self-contained or system-level calibration capabilities allow for high performance and high yield.

A 5-GHz direct-conversion CMOS transceiver utilizing automatic frequency control for the IEEE 802.11a wireless LAN standard

A 11.7mm/sup 2/ 5GHz direct-conversion 0.18/spl mu/m CMOS transceiver achieves a sensitivity of -93dBm, a system NF of 4.5dB (high gain), and IIP3 of -4.8dBm (low gain). Dissipation is 150mW in RX mode and 380mW while transmitting 15dBm OFDM signal.

Direct-conversion CMOS transceiver with automatic frequency control for 802.11a wireless LANs

/pdf/an-integrated-gsm-dect-receiver-design-specifications-3t0cl5o5dk.pdf

An Integrated GSM/DECT Receiver: Design Specifications

High-performance phase-locked-loops (PLLs) are key building blocks for many modern ICs. The sub-sampling PLL proposed in [1] uses a reference clock REF to sample a high-frequency VCO and converts phase/timing error into voltage. The steep dv/dt slope of the VCO helps to realize a high phase-detection gain and greatly suppresses the noise of loop components succeeding the phase detector, leading to low in-band phase noise and good PLL Figure-Of-Merit (FOM). However, the original design in [1] is analog and limited to integer-N (int-N) operation. It is desirable to extend it to more versatile fractional-N (frac-N) mode, and to make it digital for greater flexibility and more advanced digital calibration. This work presents a new 28nm CMOS digital frac-N sampling PLL design that achieved 0.16ps rms jitter with 8.2mW and a state-of-the-art frac-N PLL FOM of −246.8dB.

Li Lin

Papers

A 1.75 GHz highly-integrated narrow-band CMOS transmitter with harmonic-rejection mixers

A 5-GHz direct-conversion CMOS transceiver utilizing automatic frequency control for the IEEE 802.11a wireless LAN standard

Direct-conversion CMOS transceiver with automatic frequency control for 802.11a wireless LANs

An Integrated GSM/DECT Receiver: Design Specifications

9.6 A 2.7-to-4.3GHz, 0.16psrms-jitter, −246.8dB-FOM, digital fractional-N sampling PLL in 28nm CMOS