The field of nanomagnetism has recently attracted tremendous attention as it can potentially deliver low-power, high-speed and dense non-volatile memories. It is now possible to engineer the size, shape, spacing, orientation and composition of sub-100 nm magnetic structures. This has spurred the exploration of nanomagnets for unconventional computing paradigms. Here, we harness the energy-minimization nature of nanomagnetic systems to solve the quadratic optimization problems that arise in computer vision applications, which are computationally expensive. By exploiting the magnetization states of nanomagnetic disks as state representations of a vortex and single domain, we develop a magnetic Hamiltonian and implement it in a magnetic system that can identify the salient features of a given image with more than 85% true positive rate. These results show the potential of this alternative computing method to develop a magnetic coprocessor that might solve complex problems in fewer clock cycles than traditional processors. Arrays of circular nanomagnets are used to solve the problem of perceptual organization in computer vision by exploiting their tendency to minimize the total magnetic energy by coupling to each other.

Non-Boolean computing with nanomagnets for computer vision applications

In the post-CMOS scenario, field coupled nanotechnologies represent an innovative and interesting new direction for electronic nanocomputing. Among these technologies, nanomagnet logic (NML) makes it possible to finally embed logic and memory in the same device. To fully analyze the potential of NML circuits, design tools that mimic the CMOS design-flow should be used for circuit design. We present, in this paper, the latest and improved version of Torino Politecnico Nanotechnology (ToPoliNano), our design and simulation framework for field coupled nanotechnologies. ToPoliNano emulates the top-down design process of CMOS technology. Circuits are described with a VHSIC hardware description language netlist and layout is then automatically generated considering in-plane NML (iNML) technology. The resulting circuits can be simulated and performance can be analyzed. In this paper, we describe several enhancements to the tool itself, like a circuit editor for custom design of field coupled nanodevices, improved algorithms for netlist optimization and new algorithms for the place and route of iNML circuits. We have validated and analyzed the tool by using extensive metrics, both by using standard circuits and ISCAS’85 benchmarks. This contribution highlights the improvements of ToPoliNano, which is now a innovative and complete tool for the development of iNML technology.

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ToPoliNano: A CAD Tool for Nano Magnetic Logic

Magnetic Quantum Dot Cellular Automata (MQCA) have been recently proposed as an attractive implementation of QCA as a possible CMOS technology substitute. Marking a difference with respect to previous contributions, in this work we show that it is possible to develop and describe complex MQCA computational blocks strongly linking technology and having in mind a feasible realization. Thus, we propose a practicable clock structure for MQCA baptised “snake-clock”, we stick to this while developing a system level Hardware Description Language (HDL) based description of an architectural block, and we suggest a delay insensitive Null Convention LogicTM (NCL, [1]) implementation for the magnetic case so that the “layout=timing” problem can be solved. Furthermore we include in our model aspects critically related to technology and real production, that is timing, power and layout, and we present the preliminary steps of our experiments, the results of which will be included in the architecture description.

A technology aware magnetic QCA NCL-HDL architecture

In most computational systems memory access represents a relevant bottleneck for circuits performance. The execution speed of algorithms is severely limited by memory access time. An emerging technology like Nano Magnet Logic (NML), where its magnetic nature leads to an intrinsic memory ability, represents therefore a very promising opportunity to solve this issue. Nano Magnet Logic is the ideal candidate to implement the so called Logic-In-Memory (LIM) architecture. But how is it possible to organize an architecture where logic and memory are mixed and not separated entities? In this paper we try to address this issue presenting our recent developments on LIM architectures. We originally conceived a LIM architecture without considering any technological constraints. Here we present the first adaptation of that architecture to Nano Magnet Logic technology. The architecture is based on an array of identical cells developed on three virtual layers, one for logic, one for memory and one for information routing. These three virtual layers are mapped on two physical layers exploiting all our recent improvements on Nano Magnet Logic technology, which are validated with the help of low level simulations. The structure has been tested implementing two different algorithms, a sort algorithm and an image manipulation algorithm. A complete characterization in terms of area and power is reported. The structure here presented is therefore the first step of an ongoing effort directed toward the development of truly innovative architectures.

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Logic-in-Memory: A Nano Magnet Logic Implementation

The current trend for intensive computational architectures is to adopt massive parallelism, with several concurrent tasks performed simultaneously, as done for example in GPUs. This approach has many advantages, such as the reduced design time given by circuit replication and an increasing in computational speed without the need of higher frequency. It has however evidenced an important bottleneck in data exchange between memory and processor. We envisage a revolutionary path for the future relation between memory and logic in parallel processors, where a new type of architecture exploits the principle of caching to the limit. Our Logic-in-Memory (LIM) architecture mixes logic and memory in the same device, removing the bottleneck of other existing parallel solutions. The architecture we propose, here in its preliminary version, has an array organization and each element in the array is based on three blocks: a logic unit for processing, a smart memory block and a routing structure for inter block communication. In this article we show the benefits of this approach with an application example in the image processing field. We can achieve a 4X computational time reduction for an image processing algorithm (Summed Area Table) with respect to the best architecture present in the literature, even with a preliminary and not optimized version. Besides the adoption of massive parallelism to increase performance, new technologies to open the post-CMOS era are explored. Among them NanoMagnet Logic (NML) is particularly interesting for its ability to mix logic and memory in the same device. We present here the preliminary results of the NML implementation of the LIM architecture. We thus demonstrate that it is not only a good solution for a standard CMOS technology but can also exploit the potential of an emerging technology as NML.

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Logic-in-Memory architecture made real

In recent years, magnetic-based technologies, like nanomagnet logic (NML), are gaining increasing interest as possible substitutes of CMOS transistors. The possibility to mix logic and memory in the same device, coupled with a potential low power consumption, opens up completely new ways of developing circuits. The major issue of this technology is the necessity to use an external magnetic field as clock signal to drive the information through the circuit. The power losses due to the magnetic field generation potentially wipe out any advantages of NML. To solve this problem, new clock mechanisms were developed, based on spin transfer torque current and on voltage-controlled multiferroic structures that use magnetoelastic properties of magnetic materials, i.e., exploiting the possibility of influencing magnetization dynamics by means of the elastic tensor. In particular, the latter shows an extremely low power consumption. In this paper, we propose an innovative voltage-controlled magnetoelastic clock system aware of the technological constraints risen by modern fabrication processes. We show how circuits can be fabricated taking into account technological limitations, and we evaluate the performance of the proposed system. Results show that the proposed solution promises remarkable improvements over other NML approaches, even though state-of-the-art ideal multiferroic logic has in theory better performance. Moreover, since the proposed approach is technology-friendly, it gives a substantial contribution toward the fabrication of a full magnetic circuit and represents an optimal tradeoff between performance and feasibility.

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Luca Di Crescenzo

Papers

Magnetoelastic Clock System for Nanomagnet Logic