Showing papers by "Luca Sterpone published in 2013"

A Novel Fault Tolerant and Runtime Reconfigurable Platform for Satellite Payload Processing

Abstract: Reconfigurable hardware is gaining a steadily growing interest in the domain of space applications. The ability to reconfigure the information processing infrastructure at runtime together with the high computational power of today's FPGA architectures at relatively low power makes these devices interesting candidates for data processing in space applications. Partial dynamic reconfiguration of FPGAs enables maximum flexibility and can be utilized for performance optimization, for improving energy efficiency, and for enhanced fault tolerance. To be able to prove the effectiveness of these novel approaches for satellite payload processing, a highly scalable prototyping environment has been developed, combining dynamically reconfigurable FPGAs with the required interfaces such as SpaceWire, MIL-STD-1553B, and SpaceFibre. The developed systems have been enabled to space harsh environments thanks to an analytical analysis of the radiation effects on its most critical reconfigurable components. Aiming at that scope, a new algorithm for the analysis of critical radiation effects, in particular, related to Single Event Upsets (SEUs) and Multiple Event Upsets (MEUs) has been developed to obtain an effective estimation of the radiation impact and enabling the tuning of the component mapping reducing the routing interaction between the reconfigurable placed modules in their different feasible positions. The experimental performance of the system has been evaluated by a proper dynamic reconfiguration scenario, demonstrating a partial reconfiguration at 400 MByte/s, blind and readback scrubbing is supported and the scrub rate can be adapted individually for different parts of the design. The fault tolerance capability has been proven by means of a new analysis algorithm and by fault injection campaigns of SEUs and MCUs into the FPGA configuration memory.

An error-detection and self-repairing method for dynamically and partially reconfigurable systems

Abstract: Reconfigurable systems are gaining an increasing interest in the domain of safety-critical applications, for example in space and avionic applications. In fact, the capability of reconfiguring the system during run-time execution and the high computational power of modern Field Programmable Gate Arrays (FPGAs) makes these devices suitable for data processing. Moreover, such systems must also guarantee the abilities of self-awareness, self-diagnosis and self-repair in order to cope with errors due to the harsh conditions typically existing in some environments. In this paper we propose a self-repairing method for partially and dynamically reconfigurable systems applied at a fine-grain granularity level. Our method is able to recover and correct errors using the run-time partial reconfiguration capabilities offered by modern SRAM-based FPGAs. Fault injection experiments have been executed on a dynamically reconfigurable system embedding a number of benchmark circuits. Results demonstrate that the method can achieve full detection of single and multiple errors, while significantly improving the system availability with respect to traditional error detection and correction methods.

On the optimal reconfiguration times for TMR circuits on SRAM based FPGAs

Abstract: Unreliable and harsh environmental conditions in avionics and space applications demand run-time adaptation capabilities to withstand environmental changes and radiation-induced faults. Modern SRAM-based FPGAs integrating high computational power with partial and dynamic reconfiguration abilities are a usual candidate for such systems. However, due to the vulnerability of these devices to Single Event Upsets (SEUs), designs need proper fault-handling mechanisms. In this work we propose a novel circuit instrumentation method for probing Triple Modular Redundancy (TMR) circuits for error detection at the granularity of individual domains and then use selective run-time dynamic reconfiguration for recovery. Error detection logic is inserted in the physical net-list to identify and localize faults. Moreover, selective domain reconfiguration is achieved by careful considerations in the placement phase on the FPGA reconfigurable area. The proposed technique is suitable for systems having hard real-time constraints. Our results demonstrate that this approach has an overhead of 2 LUTs per majority voter in internal partitions in terms of area when compared to the standard TMR circuits. In addition, it brings down the reconfiguration times of TMR circuits to a single domain and ensures a 100% availability of the device assuming the Single Event Upset fault model.

On the evaluation of soft-errors detection techniques for GPGPUs

Abstract: Recently, General Purpose Graphic Processing Units (GPGPUs) have begun to be preferred to CPUs for several computationally intensive applications, not necessarily related to computer graphics. However, due to their complexity GPGPUs also show a relatively high sensitivity to soft errors. Hence, there is some interest in devising and applying software techniques able to exploit their computational power by just acting on the executed code. In this paper we report some preliminary results obtained by applying two different software redundancy techniques aimed at soft-error detection; these techniques are completely algorithm independent, and have been applied on a sample application running on a Commercial-Off-The-Shelf GPGPU. The results have been gathered resorting to a neutron testing campaign. Some experimental results, explaining the capabilities of the methods, are presented and commented.

Unexcitability analysis of SEus affecting the routing structure of SRAM-based FPGAs

Abstract: Testing SEUs in the configuration memory of SRAM-based FPGAs is very costly due to their large configuration memory, therefore it is necessary to optimize the generation of test patterns. In particular, in order to reduce the effort required of automatic test pattern generators, it is useful to identify early the unexcitable faults, i.e., those faults that cannot be excited by any combination of input signals. In this paper, the unexcitability of SEUs affecting the configuration bits controlling the routing resources of SRAM-based FPGAs is considered. Since this part of the configuration memory contains the largest number of configuration bits, its testing is particularly onerous. Faults in the routing resources are modeled considering the actual electrical behavior of the affected interconnections, thus the resulting fault model is more accurate than the classical open/short model usually considered. This paper introduces a methodology to prove the unexcitability of these faults. The methodology has been implemented in a tool based on a formal specification language (SAL) and a model checker (SAL-SMC). Results from the application of the tool to some circuits from the ITC'99 benchmark are reported.

On-line testing of permanent radiation effects in reconfigurable systems

Abstract: Partially reconfigurable systems are more and more employed in many application fields, including aerospace. SRAM-based FPGAs represent an extremely interesting hardware platform for this kind of systems, because they offer flexibility as well as processing power. In this paper we report about the ongoing development of a software flow for the generation of hard macros for on-line testing and diagnosing of permanent faults due to radiation in SRAM-FPGAs used in space missions. Once faults have been detected and diagnosed the flow allows to generate fine-grained patch hard macros that can be used to mask out the discovered faulty resources, allowing partially faulty regions of the FPGA to be available for further use.

Exploiting the debug interface to support on-line test of control flow errors

Abstract: Detecting the effects of transient faults is a key point in many safety-critical applications. This paper explores the possibility of using for this purpose the debug interface existing today in several processors/controllers on the market. In this way one can achieve a good detection capability with respect to control flow errors with very small latency, while the cost for adopting the proposed technique is rather limited and does not involve any change either in the processor hardware or in the application software. The method works even if the processor uses caches. Experimental results are reported, showing both the advantages and the costs of the method.

Validation and robustness assessment of an automotive system

Abstract: Due to the growing complexity of automotive systems, including various modules (e.g., microcontrollers, DSPs, memories and IP cores), validation and debug have become increasingly complex, with consequent impact on time-to-market and quality. In this paper we propose a novel flow for hardware and software validation and debug through the use of an FPGA-based emulation platform, which provides a valuable support for these important phases of the development flow. The same emulation platform is also able to support faults injection in the device under validation. Fault injection is intended not only to provide an evaluation of the system fault tolerance, but also to support the debug of the embedded fault tolerance mechanisms. Experimental results on a real industrial case study allow to evaluate the effectiveness and costs of the proposed solution.

Dynamic neutron testing of Dynamically Reconfigurable Processing Modules architecture

Abstract: The usage of reconfigurable systems is of increasingly interest for space and avionic applications. In the present work we propose an implementation flow for hardening Dynamically Reconfigurable Processing Module (DRPM) Systems implemented on modern SRAM-based FPGAs. We also report neutron radiation testing campaigns when the system is implemented on Xilinx Virtex-4 and Virtex-5 SRAM-based FPGAs. Experimental results performed by heavy-ions radiation experiments and fault injection campaigns demonstrate the effectiveness of the proposed method.

Power Consumption Versus Configuration SEUs in Xilinx Virtex-5 FPGAs

Abstract: SEUs in the configuration memory are the major cause of faults in SRAM-based FPGAs exposed to radiation. Most of the research about this topic focuses on studying the mechanism of random changes in the FPGA resources (logic blocks, flip-flops, IO, and interconnection network) for their impact on the overall device reliability and fault analysis, while much less effort has been spent in evaluating the effects of SEUs on power consumption. In this paper, we present a detailed analysis of the power consumption of a Xilinx Virtex 5 LX50T on the CORE, AUX, MGT and IO domains during irradiation with 62-MeV proton beams. The tests have been performed at the Superconductive Cyclotron of the LNS-INFN facility (Catania, Italy). Changes in power consumption (most notably in the logic core) are experienced. We present an analysis of the current trends and the results of fault injection tests, on the programmable routing resources, aimed at confirming or excluding possible fault mechanisms for the SEU-induced current variations.

On the development of diagnostic test programs for VLIW processors

Abstract: Software-Based Self-Test (SBST) approaches have shown to be an effective solution to detect permanent faults, both at the end of the production process, and during the operational phase. When partial reconfiguration is adopted to deal with permanent faults, we also need to identify the faulty module, which is then substituted with a spare one. Software-based Diagnosis techniques can be exploited for this purpose, too. When Very Long Instruction Word (VLIW) processors are addressed, these techniques can effectively exploit the parallelism intrinsic in these architectures. In this paper we propose a new approach that starting from existing detection-oriented programs generates a diagnosis-oriented test program which in most cases is able to identify the faulty module. Experimental results gathered on a case study show the effectiveness of the proposed approach.

Accurate Mitigation of Single Event Effects on Flash-based FPGAs: A new Design Flow

Abstract: We propose a new design flow for implementing circuits hardened against SET effects af- fecting Flash-based FPGAs Experimental results on RISC microprocessors show an in- crease of robustenss of more than 70% wrt traditional mitigation approaches

Partition-Based Faults Diagnosis of a VLIW Processor

Abstract: Reconfigurable systems are increasingly used in different domains, due to the advantages they offer in terms of flexibility: reconfigurability can also be used for managing possible faults affecting a circuit, when fault tolerance is the target. In this case the system must be able to (1) detect any possible fault, (2) identify the module (or partition) including it, and (3) take proper actions able to overcome the problem (e.g., by substituting the faulty module with a spare one). In this chapter, we address the point (2) when a Very Long Instruction Word (VLIW) processor is used by resorting to a Software-Based Self-Test (SBST) approach. SBST techniques have shown to represent an effective solution for permanent fault detection and diagnosis, both at the end of the production process, and during the operational phase. When VLIW processors are addressed, SBST techniques can effectively exploit the parallelism intrinsic in these architectures. In this chapter, we propose a new approach that starting from existing detection-oriented programs generates a diagnosis-oriented test program. Moreover, we propose (1) a detailed analysis of the generated equivalence classes and (2) a solution aimed to maximize the diagnosability of the modules composing the VLIW processor under test, thus perfectly suiting the needs of reconfigurable systems. Experimental results gathered on a case study VLIW processor show the effectiveness of the proposed approach: at the end of the presented method, the faulty module is always identified.