Neuromorphic computing has come to refer to a variety of brain-inspired computers, devices, and models that contrast the pervasive von Neumann computer architecture This biologically inspired approach has created highly connected synthetic neurons and synapses that can be used to model neuroscience theories as well as solve challenging machine learning problems The promise of the technology is to create a brain-like ability to learn and adapt, but the technical challenges are significant, starting with an accurate neuroscience model of how the brain works, to finding materials and engineering breakthroughs to build devices to support these models, to creating a programming framework so the systems can learn, to creating applications with brain-like capabilities In this work, we provide a comprehensive survey of the research and motivations for neuromorphic computing over its history We begin with a 35-year review of the motivations and drivers of neuromorphic computing, then look at the major research areas of the field, which we define as neuro-inspired models, algorithms and learning approaches, hardware and devices, supporting systems, and finally applications We conclude with a broad discussion on the major research topics that need to be addressed in the coming years to see the promise of neuromorphic computing fulfilled The goals of this work are to provide an exhaustive review of the research conducted in neuromorphic computing since the inception of the term, and to motivate further work by illuminating gaps in the field where new research is needed

A Survey of Neuromorphic Computing and Neural Networks in Hardware.

http://ieeexplore.ieee.org/iel5/5/31324/01456901.pdf

Microelectronic circuits

This expanded and thoroughly revised edition of Thomas H. Lee's acclaimed guide to the design of gigahertz RF integrated circuits features a completely new chapter on the principles of wireless systems. The chapters on low-noise amplifiers, oscillators and phase noise have been significantly expanded as well. The chapter on architectures now contains several examples of complete chip designs that bring together all the various theoretical and practical elements involved in producing a prototype chip. First Edition Hb (1998): 0-521-63061-4 First Edition Pb (1998); 0-521-63922-0

The Design of CMOS Radio-Frequency Integrated Circuits: RF CIRCUITS THROUGH THE AGES

An ultra-low-voltage ultra-low-power CMOS Miller operational transconductance amplifier (OTA) with rail-to-rail input/output swing is presented The topology is based on combining bulk-driven differential pair and dc level shifters, with the transistors work in weak inversion The improved Miller OTA has been successfully verified in a standard 035-mum CMOS process Experimental results have confirmed that, at a minimum supply voltage of 600 mV, lower than the threshold voltage, the topology presents almost rail-to-rail input and output swings and consumes only 550 nW

An Ultra-Low-Voltage Ultra-Low-Power CMOS Miller OTA With Rail-to-Rail Input/Output Swing

This paper presents a 60-dB gain bulk-driven Miller OTA operating at 0.25-V power supply in the 130-nm digital CMOS process. The amplifier operates in the weak-inversion region with input bulk-driven differential pair sporting positive feedback source degeneration for transconductance enhancement. In addition, the distributed layout configuration is used for all the transistors to mitigate the effect of halo implants for higher output impedance. Combining these two approaches, we experimentally demonstrate a high gain of over 60-dB with just 18-nW power consumption from 0.25-V power supply. The use of enhanced bulk-driven differential pair and distributed layout can help overcome some of the constraints imposed by nanometer CMOS process for high performance analog circuits in weak inversion region.

A 60-dB Gain OTA Operating at 0.25-V Power Supply in 130-nm Digital CMOS Process

This paper presents a high gain bulk-driven Miller OTA operating at just 0.25-V power supply in a 130-nm digital CMOS process. The amplifier operates in weak-inversion region with input bulk-driven differential pair with negative resistance source degeneration. In addition, distributed layout configuration is used for all transistors to mitigate the effect of halo implants for higher output impedance. Combining these two approaches, we experimentally demonstrate a high gain of over 60-dB with just 18-nW power consumption from 0.25-V power supply.

A 60-dB Gain OTA operating at 0.25-V power supply in 130-nm digital CMOS process

In this paper an ultra-low-power CMOS symmetrical operational transconductance amplifier (OTA) for low-frequency G m -C applications in weak inversion is presented. Its common mode input range and its linear input range can be made large using DC shifting and bulk-driven differential pair configuration (without using complex approaches). The symmetrical OTA was successfully verified in a standard CMOS 0.35-μm process. The measurements show an open loop gain of 61 dB and a unit gain frequency of 195 Hz with only 800 mV of power supply voltage and just 40 nW of power consumption. The transconductance is 66 nS, which is suitable for low-frequency G m -C applications.

An ultra-low-power CMOS symmetrical OTA for low-frequency Gm-C applications

This paper presents a 0.25-V supplied bulk-driven symmetrical OTA implemented in 130-nm CMOS process. By operating in weak inversion, and using a distributed layout approach, the OTA can benefit from the voltage reduction and high linearity enabled by halo-implanted transistors. The proposed circuit consumes only 10-nW, features a low transconductance of 22-nS, and a total harmonic distortion of 0.53 % for a 100-mVpp input voltage, thus making it suitable for low-frequency and low-power $$G_m$$ G m -C applications.

Luis H. C. Ferreira

Papers

An Ultra-Low-Voltage Ultra-Low-Power CMOS Miller OTA With Rail-to-Rail Input/Output Swing

A 60-dB Gain OTA Operating at 0.25-V Power Supply in 130-nm Digital CMOS Process

A 60-dB Gain OTA operating at 0.25-V power supply in 130-nm digital CMOS process

An ultra-low-power CMOS symmetrical OTA for low-frequency Gm-C applications

A 0.25-V 22-nS symmetrical bulk-driven OTA for low-frequency $$G_m$$Gm-C applications in 130-nm digital CMOS process