An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

The fact that wide bandgap semiconductors are capable of electronic functionality at much higher temperatures than silicon has partially fueled their development, particularly in the case of SiC. It appears unlikely that wide bandgap semiconductor devices will find much use in low-power transistor applications until the ambient temperature exceeds approximately 300/spl deg/C, as commercially available silicon and silicon-on-insulator technologies are already satisfying requirements for digital and analog VLSI in this temperature range. However practical operation of silicon power devices at ambient temperatures above 200/spl deg/C appears problematic, as self-heating at higher power levels results in high internal junction temperatures and leakages. Thus, most electronic subsystems that simultaneously require high-temperature and high-power operation will necessarily be realized using wide bandgap devices, once they become widely available. Technological challenges impeding the realization of beneficial wide bandgap high ambient temperature electronics, including material growth, contacts, and packaging, are briefly discussed.

High-temperature electronics - a role for wide bandgap semiconductors?

Power semiconductor devices are key components in power conversion systems. Silicon carbide (SiC) has received increasing attention as a wide-bandgap semiconductor suitable for high-voltage and low-loss power devices. Through recent progress in the crystal growth and process technology of SiC, the production of medium-voltage (600?1700 V) SiC Schottky barrier diodes (SBDs) and power metal?oxide?semiconductor field-effect transistors (MOSFETs) has started. However, basic understanding of the material properties, defect electronics, and the reliability of SiC devices is still poor. In this review paper, the features and present status of SiC power devices are briefly described. Then, several important aspects of the material science and device physics of SiC, such as impurity doping, extended and point defects, and the impact of such defects on device performance and reliability, are reviewed. Fundamental issues regarding SiC SBDs and power MOSFETs are also discussed.

https://iopscience.iop.org/article/10.7567/JJAP.54.040103/pdf

Material science and device physics in SiC technology for high-voltage power devices

Silicon carbide (SiC) offers significant advantages for power-switching devices because the critical field for avalanche breakdown is about ten times higher than in silicon. SiC power devices have made remarkable progress in the past five years, demonstrating currents in excess of 100 A and blocking voltages in excess of 19000 V. In this paper we describe the latest progress in three classes of SiC devices: diodes (p-i-n and Schottky), transistors (junction field-effect transistor, metal-oxide-semiconductor field-effect transistor, and bipolar junction transistor), and thyristors (gate turn-off).

SiC power-switching devices-the second electronics revolution?

We have observed significant instability in the threshold voltage of 4H-SiC metal-oxide-semiconductor field-effect transistors due to gate-bias stressing. This effect has a strong measurement time dependence. For example, a 20-mus-long gate ramp used to measure the I-V characteristic and extract a threshold voltage was found to result in a instability three to four times greater than that measured with a 1-s-long gate ramp. The VT instability was three times greater in devices that did not receive a NO postoxidation anneal compared with those that did. This instability effect is consistent with electrons directly tunneling in and out of near-interfacial oxide traps, which in irradiated Si MOS was attributed to border traps.

Time Dependence of Bias-Stress-Induced SiC MOSFET Threshold-Voltage Instability Measurements

Results presented in this letter demonstrate that the effective channel mobility of lateral, inversion-mode 4H-SiC MOSFETs is increased significantly after passivation of SiC/SiO/sub 2/ interface states near the conduction band edge by high temperature anneals in nitric oxide. Hi-lo capacitance-voltage (C-V) and ac conductance measurements indicate that, at 0.1 eV below the conduction band edge, the interface trap density decreases from approximately 2/spl times/10/sup 13/ to 2/spl times/10/sup 12/ eV/sup -1/ cm/sup -2/ following anneals in nitric oxide at 1175/spl deg/C for 2 h. The effective channel mobility for MOSFETs fabricated with either wet or dry oxides increases by an order of magnitude to approximately 30-35 cm/sup 2//V-s following the passivation anneals.

Improved inversion channel mobility for 4H-SiC MOSFETs following high temperature anneals in nitric oxide

Fast neutron response measurements are reported for radiation detectors based on large-volume SiC p-i-n diodes. Multiple reaction peaks are observed for 14-MeV neutron reactions with the silicon and carbon nuclides in the SiC detector. A high degree of linearity is observed for the /sup 28/Si(n,/spl alpha//sub i/) reaction set of six energy levels in the product /sup 25/Mg nucleus, and pulse height defect differences between the observed /sup 12/C(n,/spl alpha//sub 0/)/sup 28/ Si(n,/spl alpha//sub i/) energy responses are discussed. Energy spectrometry applications in fission and fusion neutron fields are also discussed.

The fast neutron response of 4H silicon carbide semiconductor radiation detectors

Fast neutron response measurements are reported for radiation detectors based on large-volume SiC p-i-n diodes. Multiple reaction peaks are observed for 14-MeV neutron reactions with the silicon and carbon nuclides in the SiC detector. A high degree of linearity is observed for the /sup 28/Si(n,/spl alpha//sub 1/) reaction set of six energy levels in the product /sup 25/Mg nucleus, and pulse height defect differences between the observed /sup 12/C(n,/spl alpha//sub 0/) and /sup 28/Si(n,/spl alpha//sub 1/) energy responses are discussed. Energy spectrometry applications in fission and fusion neutron fields are also discussed.

The fast neutron response of silicon carbide semiconductor radiation detectors

This paper describes the design and fabrication of 4H-SiC, n-channel Power MOSFETs. For the first time, we have achieved 350 V, 10 A (V/sub F/=4.4 V) devices with an active area of 0.105 cm/sup 2/ (3.3 mm /spl times/3.3 mm). This represents a specific on-resistance of 43 m/spl Omega//spl middot/cm/sup 2/ for a cell pitch of 25 /spl mu/m (160,000 cells/cm/sup 2/). We have also achieved R/sub on,sp/=23 m/spl Omega//spl middot/cm/sup 2/ on smaller cells with a cell pitch of 16 /spl mu/m (390,000 cells/cm/sup 2/). An important issue in 4H-SiC MOSFETs is extremely low effective channel mobility (/spl mu//sub neff/) in the implanted p-well regions. It is shown that Al-implanted p-wells require at least 1600/spl deg/C activation anneal to achieve reasonable bulk hole mobility. Annealing at high temperatures causes surface roughness which degrades /spl mu//sub neff/ compared to low power MOSFETs made on a p-epilayer. NO annealing of the gate oxide and a buried channel structure are used for increasing /spl mu//sub neff/. A Buried channel (BC) structure with 1.7/spl times/10/sup 12/ cm/sup -2/ charge in the channel showed a high /spl mu//sub neff/ (195 cm/sup 2//V/spl middot/s) utilizing bulk buried channel, but resulted in a normally-on device. However, it is shown that by controlling the charge in the BC layer, a normally-off device with a high /spl mu//sub neff/ can be produced.

Large area 4H-SiC power MOSFETs

This paper describes the development of a nitrogen-based passivation technique for interface states near the conduction band edge [Dit(Ec)] in 4H-SiC/SiO2. These states have been observed and characterized in several laboratories for n- and p-SiC since their existence was first proposed by Schorner, et al. [1]. The origin of these states remains a point of discussion, but there is now general agreement that these states are largely responsible for the lower channel mobilities that are reported for n-channel, inversion mode 4H-SiC MOSFETs. Over the past year, much attention has been focused on finding methods by which these states can be passivated. The nitrogen passivation process that is described herein is based on post-oxidation, high temperature anneals in nitric oxide. An NO anneal at atmospheric pressure, 1175°C and 200–400sccm for 2hr reduces the interface state density at Ec-E ≅0.1eV in n-4H-SiC by more than one order of magnitude - from > 3×1013 to approximately 2×1012cm−2eV−1. Measurements for passivated MOSFETs yield effective channel mobilities of approximately 30–35cm2/V-s and low field mobilities of around 100cm2/V-s. These mobilities are the highest yet reported for MOSFETs fabricated with thermal oxides on standard 4H-SiC and represent a significant improvement compared to the single digit mobilities commonly reported for 4H inversion mode devices. The reduction in the interface state density is associated with the passivation of carbon cluster states that have energies near the conduction band edge. However, attempts to optimize the the passivation process for both dry and wet thermal oxides do not appear to reduce Dit(Ec) below about 2×1012cm−2eV−1 (compared to approximately 1010cm−2eV−1 for passivated Si/SiO2). This may be an indication that two types of interface states exist in the upper half of the SiC band gap–one type that is amenable to passivation by nitrogen and one that is not. Following NO passivation, the average breakdown field for dry oxides on p-4H-SiC is higher than the average field for wet oxides (7.6MV/cm compared to 7.1MV/cm at room temperature). However, both breakdown fields are lower than the average value of 8.2MV/cm measured for wet oxide layers that were not passivated. The lower breakdown fields can be attributed to donor-like states that appear near the valence band edge during passivation.

/pdf/nitrogen-passivation-of-the-interface-states-near-the-i65wswaenk.pdf

M.K. Das

Papers

Improved inversion channel mobility for 4H-SiC MOSFETs following high temperature anneals in nitric oxide

The fast neutron response of 4H silicon carbide semiconductor radiation detectors

The fast neutron response of silicon carbide semiconductor radiation detectors

Large area 4H-SiC power MOSFETs

Nitrogen passivation of the interface states near the conduction band edge in 4H-silicon carbide