Marco Cusmai

TL;DR: A dithering method which is mathematically shown to suppress fractional tones, in conjunction with a feedforward dither cancellation technique which suppresses dither-induced phase noise is presented.

TL;DR: This paper inspects the inter-stage coupling technique, providing design formulas, and discusses the design of each receiver block, realizing higher order filters where wider bandwidth is achieved at the expense of in-band gain ripple only.

TL;DR: A brief summary of ADPLL architectures is provided, leading to a prototype synthesizer at 3 GHz which implements a spurious tone reduction technique, and along the way, an efficient simulation model to predict fractional spur amplitude and frequency inADPLLs is presented.

TL;DR: This paper presents a power-efficient 224Gb/s-PAM-4 ADC-based receiver in a 5nm CMOS process that targets next generation Ethernet for chip-to-module applications, envisioned to be the first use-case scenario at this data-rate.

TL;DR: In this article , a 224-Gb/s PAM4 ADC-based SerDes receiver (RX) is implemented in a 5-nm FinFET process, which consists of a low-noise hybrid analog front-end (AFE) that incorporates both inductive peaking and source degeneration, a 64-way time-interleaved ADC, digital equalization consisting of an up to 30 tap feed-forward equalizer (FFE), optional decision-feedback equalizer(DFE), and a clock-data-recovery (CDR) loop utilizing a 14-GHz digitally controlled oscillator (DCO).