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Benjamin D. Parker
Researcher at IBM
Publications - 45
Citations - 1686
Benjamin D. Parker is an academic researcher from IBM. The author has contributed to research in topics: CMOS & Phase-locked loop. The author has an hindex of 19, co-authored 45 publications receiving 1556 citations. Previous affiliations of Benjamin D. Parker include Research Triangle Park.
Papers
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Proceedings ArticleDOI
A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons
Jae-sun Seo,Bernard Brezzo,Yong Liu,Benjamin D. Parker,Steven K. Esser,Robert K. Montoye,Bipin Rajendran,Jose A. Tierno,Leland Chang,Dharmendra S. Modha,Daniel J. Friedman +10 more
TL;DR: A new architecture is proposed to overcome scalable learning algorithms for networks of spiking neurons in silicon by combining innovations in computation, memory, and communication to leverage robust digital neuron circuits and novel transposable SRAM arrays.
Journal ArticleDOI
A 6.4-Gb/s CMOS SerDes core with feed-forward and decision-feedback equalization
Troy J. Beukema,Michael A. Sorna,Karl D. Selander,Steven J. Zier,Brian L. Ji,Philip John Murfet,James S. Mason,Woogeun Rhee,Herschel A. Ainspan,Benjamin D. Parker,Michael P. Beakes +10 more
TL;DR: In this paper, a two-level SerDes ASIC I/O core employing a four-tap feed-forward equalizer (FFE) in the transmitter and a five-tap decision-feedback equalizer in the receiver has been designed in 0.13-/spl mu/m CMOS.
Journal ArticleDOI
Integrated Self-Healing for mm-Wave Power Amplifiers
TL;DR: In this paper, self-healing as a technique for improving performance and yield of millimeter-wave power amplifiers against process variation and transistor mismatch, load impedance mismatch, and partial and total transistor failure is described and investigated.
Journal ArticleDOI
A Linearized, Low-Phase-Noise VCO-Based 25-GHz PLL With Autonomic Biasing
Bodhisatwa Sadhu,Mark Ferriss,Arun Natarajan,Soner Yaldiz,Jean-Olivier Plouchart,Alexander V. Rylyakov,Alberto Valdes-Garcia,Benjamin D. Parker,Aydin Babakhani,Scott Reynolds,Xin Li,Larry Pileggi,Ramesh Harjani,Tierno,Daniel Friedman +14 more
TL;DR: A prototype 25 GHz VCO based on transconductance linearization of the active devices is integrated in a dual-path PLL and achieves superior performance compared to the state of the art.
Proceedings ArticleDOI
A cycle-accurate, cycle-reproducible multi-FPGA system for accelerating multi-core processor simulation
Sameh W. Asaad,Ralph Bellofatto,Bernard Brezzo,C. Haymes,Mohit Kapur,Benjamin D. Parker,Thomas Roewer,Proshanta Saha,Todd E. Takken,Jose A. Tierno +9 more
TL;DR: A cycle-accurate and cycle-reproducible large-scale FPGA platform designed from the ground up to accelerate logic verification of the Bluegene/Q compute node ASIC, a multi-processor SOC implemented in IBM's 45 nm SOI CMOS technology.