S
S. Nakamura
Researcher at Toshiba
Publications - 24
Citations - 1092
S. Nakamura is an academic researcher from Toshiba. The author has contributed to research in topics: Gate oxide & Time-dependent gate oxide breakdown. The author has an hindex of 16, co-authored 24 publications receiving 1068 citations.
Papers
More filters
Journal ArticleDOI
1.5 nm direct-tunneling gate oxide Si MOSFET's
Hiroki Sasaki,Mizuki Ono,Takashi Yoshitomi,Tatsuya Ohguro,S. Nakamura,Masanobu Saito,Hiroshi Iwai +6 more
TL;DR: In this paper, a 1.5 nm direct-tunneling gate oxide was used to achieve a transconductance of more than 1,000 mS/mm at a gate length of 0.09 /spl mu/m at room temperature.
Journal ArticleDOI
Analysis of resistance behavior in Ti- and Ni-salicided polysilicon films
Tatsuya Ohguro,S. Nakamura,M. Koike,Toyota Morimoto,Akira Nishiyama,Y. Ushiku,Takashi Yoshitomi,Mizuki Ono,Masanobu Saito,Hiroshi Iwai +9 more
TL;DR: In this paper, the relationship between sheet resistance and line width is characterized by three distinct regions according to the value of W. The abrupt increase in sheet resistance observed in the region W/spl les/0.2 /spl mu/m cannot be explained in terms of the phase transition from C54 to C49, which is the cause of the rising resistance at larger W.
Journal ArticleDOI
Study of the manufacturing feasibility of 1.5-nm direct-tunneling gate oxide MOSFETs: uniformity, reliability, and dopant penetration of the gate oxide
Hisayo Momose,S. Nakamura,Tatsuya Ohguro,Takashi Yoshitomi,Eiji Morifuji,Toyota Morimoto,Yasuhiro Katsumata,Hiroshi Iwai +7 more
TL;DR: In this paper, the uniformity, reliability, and dopant penetration of 1.5-nm direct-tunneling gate oxide MOSFETs were investigated for the first time.
Proceedings ArticleDOI
Tunneling gate oxide approach to ultra-high current drive in small geometry MOSFETs
Hisayo Momose,Mizuki Ono,Takashi Yoshitomi,Tatsuya Ohguro,S. Nakamura,Masanobu Saito,Hiroshi Iwai +6 more
TL;DR: In this paper, the gate leakage current falls in proportion to the gate length and the drain current increases in inverse proportion, and a very high drivability of 1.1 mAspl mu/m at 15 V was obtained, with a 0.14 pm gate length.
Journal ArticleDOI
An 0.18-/spl mu/m CMOS for mixed digital and analog applications with zero-volt-V/sub th/ epitaxial-channel MOSFETs
Tatsuya Ohguro,Hiroshi Naruse,Hiroyuki Sugaya,Eiji Morifuji,S. Nakamura,Takashi Yoshitomi,Toyota Morimoto,H. Kimijima,H. Sasaki Momose,Yasuhiro Katsumata,Hiroshi Iwai +10 more
TL;DR: In this article, an undoped-epitaxial-channel MOSFET with zero-volt-V/sub-th/s for mixed high-speed digital and RF-analog applications has been developed.