A 12-bit high-speed column-parallel two-step single-slope (SS) analog-to-digital converter (ADC) for CMOS image sensors is proposed. The proposed ADC employs a single ramp voltage and multiple reference voltages, and the conversion is divided into coarse phase and fine phase to improve the conversion rate. An error calibration scheme is proposed to correct errors caused by offsets among the reference voltages. The digital-to-analog converter (DAC) used for the ramp generator is based on the split-capacitor array with an attenuation capacitor. Analysis of the DAC's linearity performance versus capacitor mismatch and parasitic capacitance is presented. A prototype 1024 × 32 Time Delay Integration (TDI) CMOS image sensor with the proposed ADC architecture has been fabricated in a standard 0.18 μm CMOS process. The proposed ADC has average power consumption of 128 μW and a conventional rate 6 times higher than the conventional SS ADC. A high-quality image, captured at the line rate of 15.5 k lines/s, shows that the proposed ADC is suitable for high-speed CMOS image sensors.

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A 12-Bit High-Speed Column-Parallel Two-Step Single-Slope Analog-to-Digital Converter (ADC) for CMOS Image Sensors

In this paper, a 120 frames per second (fps) low noise CMOS Image Sensor (CIS) based on a Two-Step Single Slope ADC (TS SS ADC) and column self-calibration technique is proposed. The TS SS ADC is suitable for high speed video systems because its conversion speed is much faster (by more than 10 times) than that of the Single Slope ADC (SS ADC). However, there exist some mismatching errors between the coarse block and the fine block due to the 2-step operation of the TS SS ADC. In general, this makes it difficult to implement the TS SS ADC beyond a 10-bit resolution. In order to improve such errors, a new 4-input comparator is discussed and a high resolution TS SS ADC is proposed. Further, a feedback circuit that enables column self-calibration to reduce the Fixed Pattern Noise (FPN) is also described. The proposed chip has been fabricated with 0.13 μm Samsung CIS technology and the chip satisfies the VGA resolution. The pixel is based on the 4-TR Active Pixel Sensor (APS). The high frame rate of 120 fps is achieved at the VGA resolution. The measured FPN is 0.38 LSB, and measured dynamic range is about 64.6 dB.

/pdf/a-two-step-a-d-conversion-and-column-self-calibration-3p825f0aso.pdf

A two-step A/D conversion and column self-calibration technique for low noise CMOS image sensors.

An ultra-linear CMOS image sensor for a high-accuracy imaging system

This article provides a practical design methodology to calculate an optimal filter for noise reduction in the readout of charge‐coupled devices (CCDs) taking into account the charge transfer and feedthroughs due to capacitive coupling in the CCD. A detailed analysis of the dynamics of the video signal and charge transfer is presented, including the circuital modeling of the output stage of the CCD and the dynamics of the electronics in the video chain before the analog‐to‐digital (AD) converter. This model is used to compute an optimal filter that minimizes the variance of the pixel noise and uses the samples of the charge transfer, before the charge is fully settled. This is necessary to enhance the performance of previous results that also use optimal filters but do not use the transition samples, while also reducing the pixel readout time, resulting in faster readouts. As a proof of concept for the optimal filter, we present novel experimental results using a Skipper CCD, which has a floating sense node that allows to measure the charge packet an arbitrary number of times. However, this technique can be applied to any CCD that has a readout system that digitally samples the video signal.

Detailed modeling of the video signal and optimal readout of charge‐coupled devices

In the paper, a single‐slope analog‐to‐digital converter (ADC) for integrated CMOS image sensor applications with an improved technique of conversion has been proposed. The proposed hybrid‐mode ADC automatically uses one of the following conversion techniques: time based (i.e. PWM) or voltage based (i.e. single‐slope). During the ADC operation, the clock frequency and reference voltage are modified in order to reduce the conversion time and achieve the optimal linearity. Owing to this, the pixel using a photodiode working in the integration mode achieves a linear photoconversion characteristics (irradiance to digital number), and the conversion period, which is determined by the darkest parts of a scene, is reduced by an order of magnitude comparing with known ADC solutions. The proposed conversion technique has been validated with the ASIC prototype of a CMOS imager containing photosensors integrated with the ADCs. The ASIC was fabricated in standard 0.18 μm CMOS technology. A specialized measurement system has been used to optimize linearity in the hybrid‐mode conversion (integral nonlinearity below 2 LSB). The conversion period has been reduced 15 times compared with the standard technique. Measurements confirm functionality of the proposed approach, implemented within a small pixel area.

Hybrid‐mode single‐slope ADC with improved linearity and reduced conversion time for CMOS image sensors

This paper presents a high-linearity pixel readout circuit and a 10-bit ADC for using in CMOS image sensor. Nonlinearity, total input referred noise power, and power consumption of the proposed readout circuit are − 60 dB, 411 nV2, and 68 µW, respectively. The proposed pixel readout circuit is suitable for use in precision CMOS imagers. All circuits have been designed using TSMC 0.18 µm 1-poly 6-metal standard CMOS process.

A highly linear and high-accurate CMOS image sensor

This paper presents a high linearity, low area and low power column-parallel readout circuit with a modified 3 transistor active pixel sensor (3T-APS). Each column readout circuit consumes 43uW power provided from the 3.3V power supply and a small layout size of 10x300um2 is integrated in the 512 columns at one side of the pixel array. The modified pixel achieves the signal saturation voltage is the same as the standard APS structure, and the readout circuit linearity range is 99.9%. A high linearity 512x512 pixel CMOS image sensor with the proposed column-parallel readout circuit is designed based on 0.35um 2P4M standard CMOS technology.

A new linear readout circuit for a CMOS image sensor

This paper presents a high speed, high resolution column-parallel ADC with global digital error correction. Proposed A/D converter is suitable for using in high-frame-rate CMOS image sensors. This new method has more valuable than conventional ramp ADC from viewpoint of speed and resolution. A prototype 11-bit ADC is implemented in 0.25µm CMOS technology. Moreover, an overall SNR of 63.8dB can be achieved at 0.5Msample/s. The power dissipation of all 320 column-parallel ADCs with the peripheral circuits consume 76mW at 2.5V supplies.

A high speed A/D converter for using in low power CMOS image sensors

This paper presents a full high definition 1920 × 1080 pixel, 120 frames/s CMOS image sensor with two-step single-slope (TS-SS) ADC. The column-parallel TS-SS ADC and binary subtractor are used to convert photodiode voltage to the final 10-bit digital data. Therefore, there is no need for the pixel readout, noise suppression or comparator offset cancellation circuits to be used in the columns. A new ramp signal generator is proposed to generate 32 concurrent and identical ramp signals. TS-SS ADC improves the conversion speed while reducing the power consumption level as well. The proposed image sensor has been designed using TSMC 0.18 μm 1-poly 4-metal standard process. The simulation results show that the total comparator referred noise to the FD node in 1 Hz–100 MHz range is 0.574 mV and, also the total power consumption is about 100 mW.

Masood Teymouri

Papers

An ultra-linear CMOS image sensor for a high-accuracy imaging system

A highly linear and high-accurate CMOS image sensor

A new linear readout circuit for a CMOS image sensor

A high speed A/D converter for using in low power CMOS image sensors

A FHD 1080, 120 fps CMOS image sensor with two step SS-ADC