An object is to provide a method for manufacturing a semiconductor device, in which the number of photolithography steps can be reduced, the manufacturing process can be simplified, and manufacturing can be performed with high yield at low cost A method for manufacturing a semiconductor device includes the following steps: forming a semiconductor film; irradiating a laser beam by passing the laser beam through a photomask including a shield for shielding the laser beam; subliming a region which has been irradiated with the laser beam through a region in which the shield is not formed in the photomask in the semiconductor film; forming an island-shaped semiconductor film in such a way that a region which is not irradiated with the laser beam is not sublimed because it is a region in which the shield is formed in the photomask; forming a first electrode which is one of a source electrode and a drain electrode and a second electrode which is the other one of the source electrode and the drain electrode; forming a gate insulating film; and forming a gate electrode over the gate insulating film

Method for Manufacturing Semiconductor Device

Provided are a semiconductor device, which can facilitate a salicide process and can prevent a gate from being damaged due to misalign, and a method of manufacturing of the semiconductor device. The method includes forming a first insulation layer pattern on a substrate having a gate pattern and a source/drain region formed at both sides of the gate pattern, the first insulation layer pattern having an exposed portion of the source/drain region, forming a silicide layer on the exposed source/drain region, forming a second insulation layer on the entire surface of the substrate to cover the first insulation layer pattern and the silicide layer, and forming a contact hole in the second insulation layer to expose the silicide layer.

Semiconductor devices and methods of manufacturing the same

The relentless drive toward high-speed and high-density silicon-based integrated circuits (ICs) has necessitated significant advances in processing technology. The entrance of copper metallization in IC manufacturing has resulted in new challenges in metal-insulator-metal (MIM) capacitor fabrication, one of the key building blocks in analog/mixed signal/RFCMOS circuits. The requirement to reduce passive chip space has led to active researches for MIM with high dielectric constant (/spl kappa/) film. This paper provides an overview of MIM capacitor integration issues with the transition from AlCu backend of line (BEOL) to Cu BEOL. The key to MIM capacitor electrical properties can be achieved with optimized dielectrics. The different MIM capacitor architectures published are also described. Special emphasis is made on the properties of various MIM with high-/spl kappa/ dielectrics in the last section.

MIM capacitor integration for mixed-signal/RF applications

Method of forming a radio frequency integrated circuit (RFIC) is provided. The RFIC comprises one or more electronic devices formed in a semiconductor substrate and one or more passive devices on a dielectric substrate, arranged in a stacking manner. Electrical shield structure is formed in between to shield electronic devices in the semiconductor substrate from the passive devices in the dielectric substrate. Vertical through-silicon-vias (TSVs) are formed to provide electrical connections between the passive devices in the dielectric substrate and the electronic devices in the semiconductor substrate.

Forming radio frequency integrated circuits

In this paper, we evaluate the high-frequency performance limitations of traditional LC voltage-controlled oscillators (VCOs) that use a cross-coupled negative resistance cell and propose a new topology that overcomes these limitations. The proposed cell is based on a capacitively emitter degenerated topology which uses a cross-coupled MOS pair as the degeneration cell. The cross-coupled MOS pair contributes additional conductance and results in a higher maximum attainable oscillation frequency and better negative resistance characteristics as compared to the other topologies at high frequencies. These properties combined with its small effective capacitance enable low-power low-noise high-frequency VCO implementations. The proposed topology is demonstrated through a 20-GHz fully integrated LC VCO implemented in the IBM SiGe 0.25-/spl mu/m BiCMOS process. A comparison of its figure of merit with previously reported 20-GHz VCOs shows the effectiveness of the proposed topology.

/spl Sigma/High-frequency LC VCO design using capacitive degeneration

This paper describes the design and technology optimization of power-efficient monolithic VCOs with wide tuning range. Four 5-GHz LC-tank VCOs were fabricated in a 0.12-/spl mu/m SOI CMOS technology that was not enhanced for RF applications. High and regular resistivity substrates were used, as were single-layer and multiple-layer copper inductors. Using a new figure-of-merit (FOM/sub T/) that encompasses power dissipation, phase noise and tuning range, our best VCO has an FOM/sub T/ of -189 dBc/Hz. The measured frequency tuning range is 22 % and the phase noise is 126 dBc/Hz at 1 MHz offset for 4.5-GHz. Oscillation was achieved at 5.4-GHz at a minimum power consumption of 500 /spl mu/W.

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A power-optimized widely-tunable 5-GHz monolithic VCO in a digital SOI CMOS technology. On high resistivity substrate

This paper presents high-Q and high-density 3-dimensional VPP (vertical parallel plate) capacitors fabricated in a 0.12 /spl mu/m SOI CMOS technology. An effective capacitance density of 1.76 fF//spl mu/m/sup 2/ is obtained. A quality-factor of 22 at 1 GHz is obtained for a 20 pF VPP capacitor. Also, a VPP capacitor model is proposed for the first time to design the VPP capacitor.

3-dimensional vertical parallel plate capacitors in an SOI CMOS technology for integrated RF circuits

A damascene wire and method of forming the wire. The method including: forming a mask layer on a top surface of a dielectric layer; forming an opening in the mask layer; forming a trench in the dielectric layer where the dielectric layer is not protected by the mask layer; recessing the sidewalls of the trench under the mask layer; forming a conformal conductive liner on all exposed surface of the trench and the mask layer; filling the trench with a core electrical conductor; removing portions of the conductive liner extending above the top surface of the dielectric layer and removing the mask layer; and forming a conductive cap on a top surface of the core conductor. The structure includes a core conductor clad in a conductive liner and a conductive capping layer in contact with the top surface of the core conductor that is not covered by the conductive liner.

Interconnect structure and method of fabrication of same

This paper presents a three-stage CML (current mode logic) ring VCO fabricated in a 0.12 /spl mu/m SOI CMOS technology with a minimum stage delay of 5.4 ps at a differential voltage swing of 400 mV. The maximum oscillation frequency measured is 31 GHz. A tuning range as high as 10% is measured. The phase noise is -95.6 dBc at an offset frequency of 10 MHz. The energy per stage is as low as 26.8 fJ at a power supply voltage of 1.5V and a delay per stage of 5.95 ps.

A 31 GHz CML ring VCO with 5.4 ps delay in a 0.12-/spl mu/m SOI CMOS technology

A method of forming a damascene wire. The method including: forming a mask layer on a top surface of a dielectric layer; forming an opening in the mask layer; forming a trench in the dielectric layer where the dielectric layer is not protected by the mask layer; recessing the sidewalls of the trench under the mask layer; forming a conformal conductive liner on all exposed surface of the trench and the mask layer; filling the trench with a core electrical conductor; removing portions of the conductive liner extending above the top surface of the dielectric layer and removing the mask layer; and forming a conductive cap on a top surface of the core conductor.

Meeyoung H. Yoon

Papers

A power-optimized widely-tunable 5-GHz monolithic VCO in a digital SOI CMOS technology. On high resistivity substrate

3-dimensional vertical parallel plate capacitors in an SOI CMOS technology for integrated RF circuits

Interconnect structure and method of fabrication of same

A 31 GHz CML ring VCO with 5.4 ps delay in a 0.12-/spl mu/m SOI CMOS technology

Method of fabrication of interconnect structures