M
Melanie J. Sherony
Researcher at IBM
Publications - 50
Citations - 904
Melanie J. Sherony is an academic researcher from IBM. The author has contributed to research in topics: CMOS & Silicon on insulator. The author has an hindex of 20, co-authored 50 publications receiving 893 citations. Previous affiliations of Melanie J. Sherony include Infineon Technologies.
Papers
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Proceedings ArticleDOI
A cost effective 32nm high-K/ metal gate CMOS technology for low power applications with single-metal/gate-first process
X. Chen,S. Samavedam,Vijay Narayanan,Kenneth J. Stein,C. Hobbs,Christopher V. Baiocco,Weipeng Li,Jaeger Daniel,M. Zaleski,Haining Yang,Nam-Sung Kim,Yi-Wei Lee,Da Zhang,Laegu Kang,J. Chen,Haoren Zhuang,Arifuzzaman (Arif) Sheikh,J. Wallner,Michael V. Aquilino,Jin-Ping Han,Zhenrong Jin,James Chingwei Li,G. Massey,S. Kalpat,Rashmi Jha,Naim Moumen,R. Mo,S. Kirshnan,X. Wang,Michael P. Chudzik,M. Chowdhury,Deleep R. Nair,C. Reddy,Young Way Teh,Chandrasekharan Kothandaraman,Douglas D. Coolbaugh,Shesh Mani Pandey,D. Tekleab,Aaron Thean,Melanie J. Sherony,Craig S. Lage,J. Sudijono,R. Lindsay,JiYeon Ku,Mukesh Khare,An L. Steegen +45 more
TL;DR: In this article, a 32 nm high-k/metal gate (HK-MG) low power CMOS platform technology with low standby leakage transistors and functional high-density SRAM with a cell size of 0.157 mum2 was demonstrated.
Proceedings ArticleDOI
Scaling of 32nm low power SRAM with high-K metal gate
H.S. Yang,Robert C. Wong,R. Hasumi,Y. Gao,Nam-Sung Kim,Deok-Hyung Lee,Sayeed A. Badrudduza,Deleep R. Nair,Martin Ostermayr,Ho-Kyu Kang,Haoren Zhuang,James Chingwei Li,Laegu Kang,X. Chen,Aaron Thean,Franck Arnaud,L. Zhuang,C. Schiller,D.P. Sun,Y.W. Teh,J. Wallner,Y. Takasu,Kenneth J. Stein,S. Samavedam,Jaeger Daniel,Christopher V. Baiocco,Melanie J. Sherony,Mukesh Khare,Craig S. Lage,J. Pape,J. Sudijono,An L. Steegen,S. Stiffler +32 more
TL;DR: In this article, the authors describe SRAM scaling for 32 nm low power bulk technology, enabled by high-K metal gate process, down to 0.149 mum2 and 0.124 mum2.
Proceedings ArticleDOI
A power-optimized widely-tunable 5-GHz monolithic VCO in a digital SOI CMOS technology. On high resistivity substrate
Jonghae Kim,Jean-Olivier Plouchart,Noah Zamdmer,Melanie J. Sherony,Yue Tan,Meeyoung H. Yoon,Robert Trzcinski,Mohamed Talbi,John M. Safran,Asit Kumar Ray,Lawrence F. Wagner +10 more
TL;DR: This paper describes the design and technology optimization of power-efficient monolithic VCOs with wide tuning range and uses a new figure-of-merit (FOMT) that encompasses power dissipation, phase noise and tuning range.
Proceedings ArticleDOI
A power-efficient 33 GHz 2:1 static frequency divider in 0.12-/spl mu/m SOI CMOS
Jean-Olivier Plouchart,Jonghae Kim,H. Recoules,Noah Zamdmer,Yue Tan,Melanie J. Sherony,Asit Kumar Ray,Lawrence F. Wagner +7 more
TL;DR: In this paper, a 2:1 static frequency divider was fabricated in a 0.12-/spl mu/m SOI CMOS technology, and the divider exhibits a maximum operating frequency of 33 GHz.
Patent
Halo-free non-rectifying contact on chip with halo source/drain diffusion
James Ibm Uk Ltd. Intell. Prop. Law Culp,Jawahar P. Nayak,Werner A. Rausch,Melanie J. Sherony,Steven H. Voldman,Noah Zamdmer +5 more
TL;DR: A semiconductor chip includes a semiconductor substrate having a rectifying contact diffusion and a non-rectifying contact diffusion as mentioned in this paper, which is a source/drain diffusion of an FET to improve resistance to punch-through.