Proceedings ArticleDOI
3-dimensional vertical parallel plate capacitors in an SOI CMOS technology for integrated RF circuits
Jonghae Kim,Jean-Olivier Plouchart,Noah Zamdmer,Melanie J. Sherony,Liang-Hung Lu,Yue Tan,Meeyoung H. Yoon,Keith A. Jenkins,Mahender Kumar,Asit Kumar Ray,Lawrence F. Wagner +10 more
- pp 29-32
TLDR
In this article, high-Q and high-density 3-dimensional VPP capacitors fabricated in a 0.12 /spl mu/m SOI CMOS technology are presented.Abstract:
This paper presents high-Q and high-density 3-dimensional VPP (vertical parallel plate) capacitors fabricated in a 0.12 /spl mu/m SOI CMOS technology. An effective capacitance density of 1.76 fF//spl mu/m/sup 2/ is obtained. A quality-factor of 22 at 1 GHz is obtained for a 20 pF VPP capacitor. Also, a VPP capacitor model is proposed for the first time to design the VPP capacitor.read more
Citations
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Journal ArticleDOI
MIM capacitor integration for mixed-signal/RF applications
TL;DR: In this paper, the authors provide an overview of MIM capacitor integration issues with the transition from AlCu backend of line (BEOL) to Cu BEOL, and different MIM capacitance architectures are described.
Journal ArticleDOI
Mismatch Characterization of Small Metal Fringe Capacitors
Vaibhav Tripathi,Boris Murmann +1 more
TL;DR: A test structure and measurement results pertaining to the characterization of single-layer, lateral-field, 0.45- fF and 1.2-fF unit metal capacitors in a 32-nm SOI CMOS process are described, confirming area scaling according to Pelgrom's matching formula.
Proceedings ArticleDOI
RFCMOS technology from 0.25/spl mu/m to 65nm: the state of the art
John J. Pekarik,David R. Greenberg,Basanth Jagannathan,R. Groves,J.R. Jones,Raminderpal Singh,Anil K. Chinthakindi,X. Wang,Matthew J. Breitwisch,Douglas D. Coolbaugh,P. Cottrell,John E. Florkey,Gregory G. Freeman,Rajendran Krishnasamy +13 more
TL;DR: This work discusses some of the challenges of implementing RF designs in CMOS, focusing on those introduced by the changing properties of FETs as technology nodes scale and devices shrink.
Journal ArticleDOI
A 4-91-GHz traveling-wave amplifier in a standard 0.12-/spl mu/m SOI CMOS microprocessor technology
Jean-Olivier Plouchart,Jonghae Kim,Noah Zamdmer,Liang-Hung Lu,Melanie J. Sherony,Y. Tan,Robert A. Groves,R. Trzcinski,M. Talbi,Asit Kumar Ray,Lawrence F. Wagner +10 more
TL;DR: This paper presents five-stage and seven-stage traveling-wave amplifiers (TWA) in a 0.12-/spl mu/m SOI CMOS technology.
Proceedings ArticleDOI
Novel CMOS low-loss transmission line structure
TL;DR: In this paper, the authors proposed a low-loss transmission line structure with stacked GCPW (S-GCPW) to reduce the loss by shaping the electric fields under the signal line.
References
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Advanced passive devices for enhanced integrated RF circuit performance
Douglas D. Coolbaugh,Ebenezer E. Eshun,Robert A. Groves,D. Hararnel,Jeffrey B. Johnson,A. Harnmad,Z.X. He,Vidhya Ramachandran,Kenneth J. Stein,S. St Ongel,S. Subbanna,Dawn Wang,Richard P. Volant,X. Wang,K. Watson +14 more
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Proceedings ArticleDOI
Capacity limits and matching properties of lateral flux integrated capacitors
R. Aparicio,Ali Hajimiri +1 more
TL;DR: Theoretical limits for the capacitance density of lateral flux and quasi-fractal capacitors are calculated in this article, which leads to two new capacitor structures with high lateral field efficiency.
Proceedings ArticleDOI
Suitability of Scaled SOI CMOS for High-Frequency Analog Circuits
Noah Zamdmer,Jean-Olivier Plouchart,Jonghae Kim,Liang-Hung Lu,S. Narasimha,P. O'Neil,Asit Kumar Ray,Melanie J. Sherony,Lawrence F. Wagner +8 more
TL;DR: In this article, the ability of SOI NMOS transistors to function as high-bandwidth amplifiers continuously improves as gate length shrinks below 50 nm, and the gate sheet resistance, which influences the FET input resistance and high-frequency noise, shows little variation and is an acceptable value (7: /square) in the Lpoly = 55 nm to 77 nm range.
Proceedings ArticleDOI
RF MIM capacitors using high-K Al/sub 2/O/sub 3/ and AlTiO/sub x/ dielectrics
TL;DR: In this paper, a record high capacitance density of 0.5 and 1.0 /spl mu/F/cm/sup 2/ are obtained for Al/sub 2/O/sub 3/ and AlTiO/Sub x/ MIM capacitors respectively, with loss tangent < 0.01 and process compatible to existing VLSI back-end integration.