Software implementations of brain-inspired computing underlie many important computational tasks, from image processing to speech recognition, artificial intelligence and deep learning applications. Yet, unlike real neural tissue, traditional computing architectures physically separate the core computing functions of memory and processing, making fast, efficient and low-energy computing difficult to achieve. To overcome such limitations, an attractive alternative is to design hardware that mimics neurons and synapses. Such hardware, when connected in networks or neuromorphic systems, processes information in a way more analogous to brains. Here we present an all-optical version of such a neurosynaptic system, capable of supervised and unsupervised learning. We exploit wavelength division multiplexing techniques to implement a scalable circuit architecture for photonic neural networks, successfully demonstrating pattern recognition directly in the optical domain. Such photonic neurosynaptic networks promise access to the high speed and high bandwidth inherent to optical systems, thus enabling the direct processing of optical telecommunication and visual data. An optical version of a brain-inspired neurosynaptic system, using wavelength division multiplexing techniques, is presented that is capable of supervised and unsupervised learning.

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All-optical spiking neurosynaptic networks with self-learning capabilities.

Traditional von Neumann computing systems involve separate processing and memory units. However, data movement is costly in terms of time and energy and this problem is aggravated by the recent explosive growth in highly data-centric applications related to artificial intelligence. This calls for a radical departure from the traditional systems and one such non-von Neumann computational approach is in-memory computing. Hereby certain computational tasks are performed in place in the memory itself by exploiting the physical attributes of the memory devices. Both charge-based and resistance-based memory devices are being explored for in-memory computing. In this Review, we provide a broad overview of the key computational primitives enabled by these memory devices as well as their applications spanning scientific computing, signal processing, optimization, machine learning, deep learning and stochastic computing. This Review provides an overview of memory devices and the key computational primitives for in-memory computing, and examines the possibilities of applying this computing approach to a wide range of applications.

Memory devices and applications for in-memory computing

A predictive MOSFET model is critical for early circuit design research. To accurately predict the characteristics of nanoscale CMOS, emerging physical effects, such as process variations and correlations among model parameters, must be included. In this paper, a new generation of predictive technology model (PTM) is developed to accomplish this goal. Based on physical models and early-stage silicon data, the PTM of bulk CMOS is successfully generated for 130- to 32-nm technology nodes, with an Leff of as low as 13 nm. The accuracy of PTM predictions is comprehensively verified: The error of I on is below 10% for both n-channel MOS and p-channel MOS. By tuning only ten primary parameters, the PTM can be easily customized to cover a wide range of process uncertainties. Furthermore, the new PTM correctly captures process sensitivities in the nanometer regime, particularly the interactions among Leff, Vth, mobility, and saturation velocity. A website has been established for the release of PTM: http://www.eas.asu.edu/~ptm

New Generation of Predictive Technology Model for Sub-45 nm Early Design Exploration

Dense crossbar arrays of non-volatile memory (NVM) devices represent one possible path for implementing massively-parallel and highly energy-efficient neuromorphic computing systems. We first revie...

https://www.tandfonline.com/doi/pdf/10.1080/23746149.2016.1259585

Neuromorphic computing using non-volatile memory

This comprehensive review summarizes state of the art, challenges, and prospects of the neuro-inspired computing with emerging nonvolatile memory devices. First, we discuss the demand for developing neuro-inspired architecture beyond today’s von-Neumann architecture. Second, we summarize the various approaches to designing the neuromorphic hardware (digital versus analog, spiking versus nonspiking, online training versus offline training) and discuss why emerging nonvolatile memory is attractive for implementing the synapses in the neural network. Then, we discuss the desired device characteristics of the synaptic devices (e.g., multilevel states, weight update nonlinearity/asymmetry, variation/noise), and survey a few representative material systems and device prototypes reported in the literature that show the analog conductance tuning. These candidates include phase change memory, resistive memory, ferroelectric memory, floating-gate transistors, etc. Next, we introduce the crossbar array architecture to accelerate the weighted sum and weight update operations that are commonly used in the neuro-inspired machine learning algorithms, and review the recent progresses of array-level experimental demonstrations for pattern recognition tasks. In addition, we discuss the peripheral neuron circuit design issues and present a device-circuit-algorithm codesign methodology to evaluate the impact of nonideal device effects on the system-level performance (e.g., learning accuracy). Finally, we give an outlook on the customization of the learning algorithms for efficient hardware implementation.

Neuro-Inspired Computing With Emerging Nonvolatile Memorys

We demonstrate a neuromorphic core with 64k-cell phase change memory (PCM) synaptic array (256 axons by 256 dendrites) with in-situ learning capability. 256 configurable on-chip neuron circuits perform leaky integrate and fire (LIF) and synaptic weight update based on spike-timing dependent plasticity (STDP). 2T-1R PCM unit cell design separates LIF and STDP learning paths, minimizing neuron circuit size. The circuit implementation of STDP learning algorithm along with 2T-1R structure enables both LIF and STDP learning to operate asynchronously and simultaneously within the array, avoiding additional complication and power consumption associated with timing schemes. We show hardware demonstration of in-situ learning with large representational capacity, enabled by large array size and analog synaptic weights of PCM cells.

NVM neuromorphic core with 64k-cell (256-by-256) phase change memory synaptic array with on-chip neuron circuits for continuous in-situ learning

The statistical distribution of random telegraph noise (RTN) has been measured and characterized in scaled PDSOI FETs down to 20nm gate length. Statistical analysis of RTN in ≫ 15 thousand nFETs shows temperature-independent long-tailed non-Gaussian distributions of noise amplitudes. Treated as equivalent threshold voltage variation (ΔV th ), the RTN distributions appear log-normal, with the ΔV th reaching ≫ 70 mV for the smalles devices. Because of the log-normal distribution, it appears that RTN V th variations may exceed random dopant fluctuation (RDF) V th variations at the ∼3 sigma level in the 22 nm generation, making RTN a very serious threat to SRAM stability at 22 nm and beyond.

Increasing threshold voltage variation due to random telegraph noise in FETs as gate lengths scale to 20 nm

We present for the first time in-depth analysis of the outstanding endurance characteristics of an ALD-based confined phase change memory (PCM) [1] with a thin metallic liner. Experimental results confirm that both the proper metallic liner and the confined pore cell structure are required for a reliability advantage. This confined PCM with a metallic liner is found to be immune to classic endurance failure mechanisms. The void-free confined PCM yields a new record endurance (2×1012 cycles) with stabilized elemental segregation that does not result in stuck-SET failure.

ALD-based confined PCM with a metallic liner toward unlimited endurance

We report a high-performance CMOS operating at 15 V with 119 ps nominal inverter delay at 006/008/spl mu/m L/sub eff/ for NMOS and PMOS Both NMOS and PMOS devices, with 36 nm inversion T/sub ox/, have the best current drive reported to date at fixed I/sub off/ Low-Vt NMOS/PMOS achieved with compensation and with no degradation in short-channel behavior result in nominal 97 ps inverter delay These devices are incorporated in a 018 /spl mu/m technology that offers a 42 /spl mu/m/sup 2/ SRAM cell and dual gate oxide for interfacing to 25 V

High-performance sub-0.08 /spl mu/m CMOS with dual gate oxide and 9.7 ps inverter delay

This paper describes the design and technology optimization of power-efficient monolithic VCOs with wide tuning range. Four 5-GHz LC-tank VCOs were fabricated in a 0.12-/spl mu/m SOI CMOS technology that was not enhanced for RF applications. High and regular resistivity substrates were used, as were single-layer and multiple-layer copper inductors. Using a new figure-of-merit (FOM/sub T/) that encompasses power dissipation, phase noise and tuning range, our best VCO has an FOM/sub T/ of -189 dBc/Hz. The measured frequency tuning range is 22 % and the phase noise is 126 dBc/Hz at 1 MHz offset for 4.5-GHz. Oscillation was achieved at 5.4-GHz at a minimum power consumption of 500 /spl mu/W.

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Asit Kumar Ray

Papers

NVM neuromorphic core with 64k-cell (256-by-256) phase change memory synaptic array with on-chip neuron circuits for continuous in-situ learning

Increasing threshold voltage variation due to random telegraph noise in FETs as gate lengths scale to 20 nm

ALD-based confined PCM with a metallic liner toward unlimited endurance

High-performance sub-0.08 /spl mu/m CMOS with dual gate oxide and 9.7 ps inverter delay

A power-optimized widely-tunable 5-GHz monolithic VCO in a digital SOI CMOS technology. On high resistivity substrate