Two-dimensional (2D) materials hold great promise for future nanoelectronics as conventional semiconductor technologies face serious limitations in performance and power dissipation for future technology nodes. The atomic thinness of 2D materials enables highly scaled field-effect transistors (FETs) with reduced short-channel effects while maintaining high carrier mobility, essential for high-performance, low-voltage device operations. The richness of their electronic band structure opens up the possibility of using these materials in novel electronic and optoelectronic devices. These applications are strongly dependent on the electrical properties of 2D materials-based FETs. Thus, accurate characterization of important properties such as conductivity, carrier density, mobility, contact resistance, interface trap density, etc is vital for progress in the field. However, electrical characterization methods for 2D devices, particularly FET-related measurement techniques, must be revisited since conventional characterization methods for bulk semiconductor materials often fail in the limit of ultrathin 2D materials. In this paper, we review the common electrical characterization techniques for 2D FETs and the related issues arising from adapting the techniques for use on 2D materials.

https://iopscience.iop.org/article/10.1088/2053-1583/abc187/pdf

Electrical characterization of 2D materials-based field-effect transistors

Bio-Inspired Photoelectric Artificial Synapse based on Two-Dimensional Ti3C2Tx MXenes Floating Gate

Human brain outperforms the current von Neumann digital computer in many aspects, such as energy efficiency and fault‐tolerance. Inspired by human brain, neuromorphic computation has attracted increasing research interest. In recent years, emerging neuromorphic devices are widely developed for neuromorphic computing. Herein, the recent progress on transistor‐based neuromorphic devices is presented. First, a brief introduction of biological synaptic and neuronal functions is given. Then operation principles and latest progress in neuromorphic transistors, including ion‐gate neuromorphic transistors, ferroelectric‐gate neuromorphic transistors, and floating‐gate neuromorphic transistors, are reviewed and discussed. At last, conclusions and prospects are given.

Recent Progress on Emerging Transistor-Based Neuromorphic Devices

2D materials with low-temperature processing hold promise for electronic devices that augment conventional silicon technology. To meet this promise, devices should have capabilities not easily achieved with silicon technology, including planar fully-depleted silicon-on-insulator with substrate body-bias, or vertical finFETs with no body-bias capability. In this work, we fabricate and characterize a device [a double-gate MoS2 field-effect transistor (FET) with hexagonal boron nitride (h-BN) gate dielectrics and a multi-layer graphene floating gate (FG)] in multiple operating conditions to demonstrate logic, memory, and synaptic applications; a range of h-BN thicknesses is investigated for charge retention in the FG. In particular, we demonstrate this device as a (i) logic FET with adjustable VT by charges stored in the FG, (ii) digital flash memory with lower pass-through voltage to enable improved reliability, and (iii) synaptic device with decoupling of tunneling and gate dielectrics to achieve a symmetric program/erase conductance change. Overall, this versatile device, compatible to back-end-of-line integration, could readily augment silicon technology.

Double-Gate MoS2 Field-Effect Transistor with a Multilayer Graphene Floating Gate: A Versatile Device for Logic, Memory, and Synaptic Applications.

Synaptic devices are expected to overcome von Neumann's bottleneck and served as one of the foundations for future neuromorphic computing. Lead halide perovskites are considered as promising photoactive materials but limited by the toxicity of lead. Herein, lead-free perovskite CsBi3I10 is utilized as a photoactive material to fabricate organic synaptic transistors with a floating-gate structure for the first time. The devices can maintain the Ilight/Idark ratio of 103 for 4 h and have excellent stability within the 30 days test even without encapsulation. Synaptic functions are successfully simulated. Notably, by combining the decent charge transport property of the organic semiconductor and the excellent photoelectronic property of CsBi3I10, synaptic performance can be realized even with an operating voltage as low as -0.01 V, which is rare among floating-gate synaptic transistors. Furthermore, artificial neural networks are constructed. We propose a new method that can simulate the synaptic weight value in multiple digit form to achieve complete gradient descent. The image recognition test exhibits thrilling recognition accuracy for both supervised (91%) and unsupervised (81%) classifications. These results demonstrate the great potential of floating-gate organic synaptic transistors in neuromorphic computing.

Artificial Synapses Based on Lead-Free Perovskite Floating-Gate Organic Field-Effect Transistors for Supervised and Unsupervised Learning.

In this article, we correlate various double-gate (DG) molybdenum disulfide (MoS2) FET architectures with the contact resistance ( ${R}_{{\text {C}}}$ ) and performance. We show that the MoS2 DGFETs can achieve near-ideal subthreshold slope and threshold voltage modulation. We demonstrate how these DGFETs enable extraction of the gate-dependent contact resistance using only two-point probe (2PP) measurements. We show that when MoS2 is either only above or below source/drain (S/D) metal contacts, only one of the two gates can modulate the contact resistance through electrostatic doping, even when both gates overlap the contacts with the associated overlap capacitance. Finally, we fabricate and characterize a new MoS2 DGFET structure in which MoS2 is both above and below the S/D contacts, to enable both gates to modulate ${R}_{{\text {C}}}$ and the channel resistance ( ${R}_{{\text {CHANNEL}}}$ ). We show that both gates of the new DGFET can reduce ${R}_{\text {C}}$ leading to higher drive current and more symmetrical gating for design flexibility. This new architecture will be useful in applications of DGFETs in signal processing including mixing and low-noise amplification.

Symmetry of Gating in Double-Gate MoS 2 FETs

Fabrication and characterization of MOSFETs having monolayer channels comprised of the transition metal dichalcogenide molybdenum disulfide (MoS2) are active areas of research. In this paper, we show that a simple and traditional MOSFET model, when including an accurate threshold voltage and gate-bias-dependent source/drain resistance, achieves a good visual fit to our measured data, in the linear regime, for a back-gated monolayer MoS2 FET. A four-point probe measurement technique is utilized to extract the accurate threshold voltage and gate-bias-dependent source/drain resistance implemented in the model.

Modeling of a Back-Gated Monolayer MoS 2 FET by Extraction of an Accurate Threshold Voltage and Gate-Bias-Dependent Source/Drain Resistance

Electronic devices with light-emitting regions composed of single layer transition metal dichalcogenides, such as tungsten diselenide (WSe2), are of great interest due to the formation of a direct bandgap at the single layer limit. Furthermore, increasing injected hole current into the single layer WSe2 is of great importance due to the resulting increase in electroluminescence. In this paper, we demonstrate a $1000\times $ increase in injected hole current into the channel region of an FET composed of a single layer WSe2 channel by incorporation of a thicker (20–30 nm) multilayer WSe2 film under the metal source contact only. By fabrication and analysis of FETs composed of single layer, bi-layer, and tri-layer WSe2 channel regions, we correlate the increase in injected hole current to a decrease in the hole Schottky barrier height at the source contact due to incorporation of the multilayer WSe2 film.

Enhanced Hole Injection Into Single Layer WSe 2

A phenomenological model, accounting for interface states at metal-semiconductor contacts, is proposed to explain particular gate-bias-dependent kinking in I-V characteristics sometimes observed in MoS2 FETs. The effect is studied in double-gate FETs by varying top-gate voltage (VTG) and bottom-gate voltage (VBG), with the MoS2 semiconductor layer overlying source/drain (S/D) metal contacts in contact regions. The kink in ID-VTG characteristics is observed for small negative VBG but not for large negative VBG. The model divides the FET into S/D and channel regions, with bias-dependent S/D resistance (RSD) and channel resistance (RCHAN), and with S/D regions having an additional interface state distribution (additional to any interface states associated with semiconductor/dielectric interfaces in the channel region) due to an imperfect metal-semiconductor interface where MoS2 overlies S/D metal. The additional interface states are modeled as a Gaussian distribution of acceptor-like states in the upper region of the semiconductor bandgap. When RSD ≥ RCHAN (VBG less negative), filling of these acceptor-like states as VTG increases creates a kink in ID-VTG characteristics since RSD is a major component of overall resistance limiting drain current, ID. Conversely, when RSD << RCHAN (VBG more negative), filling of these acceptor-like states as VTG increases does not create an ID-VTG kink since RSD is not the major component of resistance limiting ID. The model highlights 1) metal-semiconductor interface states need to be accounted for when modeling MoS2 FETs, and 2) importance of forming metal-semiconductor interfaces with low interface state density to avoid I-V kinks which are detrimental for analog applications.

/pdf/phenomenological-model-of-gate-dependent-kink-in-i-v-1ivotfe17v.pdf

Michael A. Rodder

Papers

Double-Gate MoS2 Field-Effect Transistor with a Multilayer Graphene Floating Gate: A Versatile Device for Logic, Memory, and Synaptic Applications.

Symmetry of Gating in Double-Gate MoS 2 FETs

Modeling of a Back-Gated Monolayer MoS 2 FET by Extraction of an Accurate Threshold Voltage and Gate-Bias-Dependent Source/Drain Resistance

Enhanced Hole Injection Into Single Layer WSe 2

Phenomenological Model of Gate-Dependent Kink in I-V Characteristics of MoS 2 Double-Gate FETs