Proceedings ArticleDOI
The 48-core SCC Processor: the Programmer's View
Timothy G. Mattson,Michael Riepen,Thomas Lehnig,Paul Brett,Werner Haas,Patrick Kennedy,Jason Howard,Sriram R. Vangal,Nitin Borkar,Greg Ruhl,Saurabh Dighe +10 more
- pp 1-11
TLDR
The programmer's view of this chip is described and RCCE is described: the native message passing model created for the SCC processor, an intermediate case, sharing traits of message passing and shared memory architectures.Abstract:
The number of cores integrated onto a single die is expected to climb steadily in the foreseeable future. This move to many-core chips is driven by a need to optimize performance per watt. How best to connect these cores and how to program the resulting many-core processor, however, is an open research question. Designs vary from GPUs to cache-coherent shared memory multiprocessors to pure distributed memory chips. The 48-core SCC processor reported in this paper is an intermediate case, sharing traits of message passing and shared memory architectures. The hardware has been described elsewhere. In this paper, we describe the programmer's view of this chip. In particular we describe RCCE: the native message passing model created for the SCC processor.read more
Citations
More filters
Journal ArticleDOI
T-crest
Martin Schoeberl,Sahar Abbaspour,Benny Akesson,Neil Audsley,Raffaele Capasso,Jamie Garside,Kees Goossens,Sven Goossens,Scott Hansen,Reinhold Heckmann,Stefan Hepp,Benedikt Huber,Alexander Jordan,Evangelia Kasapaki,Jens Knoop,Yonghui Li,Daniel Prokesch,Wolfgang Puffitsch,Peter Puschner,Andre Rocha,Claudio Silva,Jens Sparsø,Alessandro Tocchi +22 more
TL;DR: Within the T-CREST project the authors propose novel solutions for time-predictable multi-core architectures that are optimized for the WCET instead of the average-case execution time.
Journal ArticleDOI
Light-weight communications on Intel's single-chip cloud computer processor
TL;DR: This paper describes two communication libraries available on the Single-Chip Cloud Computer: RCCE and Rckmb, a light-weight, minimal library for writing message passing parallel applications and SCC's non-cache-coherent shared memory for transferring data between cores without needing to go off-chip.
Journal ArticleDOI
A Reliable Routing Architecture and Algorithm for NoCs
TL;DR: Vicis is a fault-tolerant architecture and companion routing protocol that is robust to a large number of permanent failures, allowing communication to continue in the face of permanent transistor failures.
Journal ArticleDOI
A framework for metamorphic malware analysis and real-time detection
TL;DR: A new framework called MARD is presented, to protect the end points that are often the last defense, against metamorphic malware, and provides automation, platform independence, optimizations for real-time performance and modularity.
Proceedings ArticleDOI
K2: a mobile operating system for heterogeneous coherence domains
TL;DR: This work identifies a shared-most OS model for multiple coherence domains: creating per-domain instances of core OS services with no shared state, while enabling other extended OS services to share state across domains.
References
More filters
Book
MPI: The Complete Reference
TL;DR: MPI: The Complete Reference is an annotated manual for the latest 1.1 version of the standard that illuminates the more advanced and subtle features of MPI and covers such advanced issues in parallel computing and programming as true portability, deadlock, high-performance message passing, and libraries for distributed and parallel computing.
Journal ArticleDOI
The Nas Parallel Benchmarks
David H. Bailey,Eric Barszcz,John T. Barton,D. S. Browning,Russell Carter,Leonardo Dagum,Rod Fatoohi,Paul O. Frederickson,T. A. Lasinski,Robert Schreiber,Horst D. Simon,V. Venkatakrishnan,Sisira Weeratunga +12 more
TL;DR: A new set of benchmarks has been developed for the performance evaluation of highly parallel supercom puters that mimic the computation and data move ment characteristics of large-scale computational fluid dynamics applications.
Journal Article
The NAS Parallel Benchmarks
TL;DR: The original NAS Parallel Benchmarks consisted of eight individual bench- mark problems, each of which focused on some aspect of scientific computing, although most of these benchmarks have much broader relevance, since in a much larger sense they are typical of many real-world computing applications.
Proceedings ArticleDOI
A 48-Core IA-32 message-passing processor with DVFS in 45nm CMOS
Jason Howard,Saurabh Dighe,Yatin Hoskote,Sriram R. Vangal,D. Finan,G. Ruhl,David Jenkins,H. Wilson,Nitin Borkar,Gerhard Schrom,Fabrice Pailet,Shailendra Jain,Tiju Jacob,Satish Yada,Sravan K. Marella,Praveen Salihundam,Vasantha Erraguntla,Michael Konow,Michael Riepen,Guido Droege,Joerg Lindemann,Matthias Gries,Thomas Apel,Kersten Henriss,Tor Lund-Larsen,Sebastian Steibl,Shekhar Borkar,Vivek De,Rob F. Van der Wijngaart,Timothy G. Mattson +29 more
TL;DR: This paper presents a prototype chip that integrates 48 Pentium™ class IA-32 cores on a 6×4 2D-mesh network of tiled core clusters with high-speed I/Os on the periphery to realize a data-center-on-a-die microprocessor architecture.
Journal ArticleDOI
An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS
Sriram R. Vangal,Jason Howard,Greg Ruhl,Saurabh Dighe,H. Wilson,James W. Tschanz,D. Finan,A. Singh,Tiju Jacob,Shailendra Jain,Vasantha Erraguntla,Clark Roberts,Yatin Hoskote,Nitin Borkar,Shekhar Borkar +14 more
TL;DR: In this paper, an integrated network-on-chip architecture containing 80 tiles arranged as an 8x10 2D array of floating-point cores and packet-switched routers, both designed to operate at 4 GHz.
Related Papers (5)
A 48-Core IA-32 message-passing processor with DVFS in 45nm CMOS
Jason Howard,Saurabh Dighe,Yatin Hoskote,Sriram R. Vangal,D. Finan,G. Ruhl,David Jenkins,H. Wilson,Nitin Borkar,Gerhard Schrom,Fabrice Pailet,Shailendra Jain,Tiju Jacob,Satish Yada,Sravan K. Marella,Praveen Salihundam,Vasantha Erraguntla,Michael Konow,Michael Riepen,Guido Droege,Joerg Lindemann,Matthias Gries,Thomas Apel,Kersten Henriss,Tor Lund-Larsen,Sebastian Steibl,Shekhar Borkar,Vivek De,Rob F. Van der Wijngaart,Timothy G. Mattson +29 more