In this paper, a new source-all-around tunnel field-effect transistor (SAA-TFET) is proposed and investigated by using TCAD simulation. The tunneling junction in the SAA-TFET is divided laterally and vertically with respect to the channel direction which provides a relatively large tunneling junction area. An n+ pocket design is also introduced around the source to enhance tunneling rates and improve the device characteristics. In addition, the gate and n+ pocket region also overlap in the vertical and the lateral directions resulting in an enhanced electric field and, in turn, the ON-state current of the SAA-TFET is highly increased compared with the conventional TFET. Promising results in terms of DC (ION, IOFF, ON/OFF current ratio and SS) and analog (cutoff frequency) performance are obtained for low (VDD = 0.5 V) and high (VDD = 1 V) supply voltages.

https://iopscience.iop.org/article/10.1088/1361-6641/ab5d86/pdf

Source-All-Around Tunnel Field-Effect Transistor (SAA-TFET): Proposal and Design

In this work, we investigate the effects of changing device parameters such as channel length and gate dielectric of n-type double gate (DG) silicon tunneling field effect transistor (TFET). As the quantization effects can alter the device performance, our objective is to minimize the effect of it on gate capacitance. Device sub-threshold slope (SS), threshold voltage and ION/IOFF the ratio are also considered to find the performance of the device. We find that DG TFET with the short channel length, high gate dielectric material, and material with effective mass equal to or more than 0.04 mo (mo is free electron mass) shows promising performance. SS of TFET is much less than 60 mV/dec, which is the limiting factor of a conventional MOSFET. The materials having an effective mass of electrons less than 0.04 mo shows step-like behaviors, which reduce the gate capacitance. As a result, the control over the gate decreases and increases the short channel effect. Our optimized device shows that for high dielectric constant gate materials, SS is 33 mV/dec, the threshold voltage is 0.71 V and ION/IOFF ratio is 109 . 

Quantization, gate dielectric and channel length effect in double-gate tunnel field-effect transistor

In this study, SCAPS-1D software is used to model and analyze the performance of various perovskite solar cells (PSCs) with diverse back contact metals, electron transport layers and hole transport layers combined with different mixed halide perovskite absorber materials CH3NH3PbI3−X Cl X and CH3NH3PbI3−X Br X for X = 1, 2. With CH3NH3PbI3−X Cl X as the absorber layer, the best performance is obtained for the configuration glass/fluorine-doped tin oxide (FTO)/indium gallium zinc oxide (IGZO)/CH3NH3PbI3−X Cl X /CuSbS2/Au for X = 1 with a fill factor (FF) of 61.83% and a power conversion efficiency of 13.31%. The device configuration glass/FTO/IGZO/CH3NH3PbI3−X Br X /CuO/Pd for X = 1 shows the best performance with a power conversion efficiency of 15.55% and FF of 71.19% for CH3NH3PbI3−X Cl X as the absorber layer. The study shows that the optimum total defect density values of the absorber layer, MAPbI3−X Cl X with X = 1 and X = 2 are 2.5 × 1013 cm−3 and 2.5 × 1014 cm−3, respectively. For the MAPbI3−X Br X absorber layer, with X = 1 and 2, the optimum defect density is found to be 1 × 1015 cm−3. The optimum dopant concentration is found to be 1.0 × 1018 cm−3and 1.0 × 1016 cm−3, respectively, for PSCs with MAPbI3−X ClX as the absorber layer, for X = 1 and 2. For PSCs with MAPbI3–X Br X as an absorber layer with X = 1 and 2, the optimum dopant density is found to be 1.0 × 1016 cm−3 each. The device is found to be stable at an operating temperature of 300 K.

Comparative performance analysis of mixed halide perovskite solar cells with different transport layers and back metal contacts

A Dual Material Double Gate Tunnel Field Effect Transistor (DMDGTFET) with reduced high-K dielectric length (LK = 15 nm) and drain electrode thickness (6 nm) is proposed and performed a TCAD simulation. The simulation result of proposed device exhibits suppression in gate-to-drain capacitance (CGD). The (CGD) is proportional to dielectric constant (e) of the gate insulator and drain-electrode thickness of device. In the proposed DMDGTFET, the reduction in drain electrode thickness and LK gives a low electron concentration (Q) and low dielectric constant (e) in channel/drain junction, respectively, which results in suppression of CGD. At VGS = 2 V, the CGD for the proposed and conventional device are 9 f F, and 7 f F, respectively. In addition, the proposed device exhibit unity current-gain cut-off frequency of 62 GHz, while it is 57 GHz for conventional device. The on-current (ION) of the proposed device is also measured as 2 × 10−5 (A/mm). Thus, the proposed DMDGTFET is potential candidate for fast switching applications without compromising on-current (ION).

Enhancement of Performance in TFET by Reducing High-K Dielectric Length and Drain Electrode Thickness

An analytical model based on physics is used to describe the potential distribution, horizontal electric field, and drain current of Two Gate Oxide with no junction MOSFET (TOX-NOJ-MOSFET) was investigated for cylindrical shape structure. The Poisson equation is used to derive the expression for cylindrical coordinate system which relies on parabolic approximation method. The combination of high k two gate oxide stack and junctionless transistor with Dual material Double gate structure performs a major role to diminish the short channel effects, propelled to increase the ION current (10−5A/μm) and decrease the leakage current IOFF of 10−14 A/μm to enhance ION/IOFF ratio to 109. To ensure the scalability and responsiveness of the system numerical simulations have been performed with various bias voltages and gate length ratios using Synopsys TCAD software and the results were well matched with analytical solutions.

Impact of two gate oxide with no junction metal oxide semiconductor field effect transistor- an analytical model

Gate dielectric scaling is a vital key to improve the steep switching characteristics of TFETs. However, scaling down the oxide thickness causes high gate leakage current that cannot be neglected. The impact of the leakage current on the device operation can cause a serious reliability problem. In this paper, we have investigated the effect of nonuniform gate oxide thickness on the current as well as the high-frequency performance of TFETs. The focus of this paper is to demonstrate how to reduce effects of gate leakage current by using a taper shape gate oxide. The IV and CV characteristics are investigated regarding different nonuniform gate oxide graded shapes. Further, the ON and OFF currents and SS, as figures of merit for low standby power application, have been analyzed. Apart from this, the RF figure of merit in terms of unit-gain cutoff frequency (fT) is investigated.

Impact of nonuniform gate oxide shape on TFET performance: A reliability issue

A modified pseudo 2D physically-based model for double-gate TFETs: Role of precise calculations of drain and source depletion regions

Impact of source doping profile on the performance of CNT TFETs and MOSFETs: design aspects for fabrication tolerance

In this letter, a planar integration using the deep trench isolation (DTI) technique is proposed to suppress the inter-well parasites in smart power integrated circuits implemented in 0.35 µm BiCMOS technology. In this technology, all devices share the same epitaxial layer. This can lead to a punch-through between power devices as well as between power and low-voltage CMOS devices. A DTI scheme is used to suppress the effect of the parasitic BJT by using a P+ retardation implant region under the deep trench isolation region. The injection ratio of the parasitic BJT is reduced by a factor between 3 and 8.5. The effect of the trench length and the retardation implant is investigated using SENTAURUS TCAD simulations. It is confirmed, through using TCAD simulations, that the amount of the collected carriers of the sensitive devices changes as a function of the trench length and the presence of the retardation implant.

Parasitic Suppression in 2D Smart Power ICs Using Deep Trench Isolation: A Simulation Study

This paper proposes a novel Si-TFET based on a tapered channel structure. The taper-channel design presented in this work provides a higher thickness at the source side than at the drain side, whereas the gate oxide is lesser at the source than at the drain side. The structure is investigated by varying the taper channel length and thickness using Silvaco TCAD simulation. It is found that, by engineering a taper length of 30 nm and thickness of 6 nm, a minimum subthreshold and ambipolar conduction as well as higher ON/OFF current ratio are achieved. The ambipolar current of the optimized structure is approximately $10^{-14}\ \mathrm{A}/\mu\ \mathrm{m}$ compared to 10−10 A/µm regarding the conventional structure. Also, the OFF current is decreased to about $10^{-17}\ \mathrm{A}/\mu\ \mathrm{m}$ with a little drop in I ON ; however, an increase in the (ON/OFF) current ratio is obtained.

Mohamed El-Banna

Papers

Impact of nonuniform gate oxide shape on TFET performance: A reliability issue

A modified pseudo 2D physically-based model for double-gate TFETs: Role of precise calculations of drain and source depletion regions

Impact of source doping profile on the performance of CNT TFETs and MOSFETs: design aspects for fabrication tolerance

Parasitic Suppression in 2D Smart Power ICs Using Deep Trench Isolation: A Simulation Study

Tapered-Shape Channel Engineering for Suppression of Ambipolar Current in TFET