Showing papers by "Mohamed I. Elmasry published in 2000"

Low-power direct digital frequency synthesis for wireless communications

Abstract: A low-power direct digital frequency synthesizer (DDFS) architecture is presented. It uses a smaller lookup table for sine and cosine functions compared to already existing systems with a minimum additional hardware. Only 16 points are stored in the internal memory implemented in ROM (read-only memory). The full computation of the generated sine and cosine is based on the linear interpolation between the sample points. A DDFS with 60-dBc spectral purity 29-Hz frequency resolution, and 9-bit output data for sine function generation is being implemented in 0.8-/spl mu/m CMOS technology. Experimental results verify that the average power dissipation of the DDFS logic is 9.5 mW (at 30 MHz, 3.3 V).

High-speed dynamic logic styles for scaled-down CMOS and MTCMOS technologies

Abstract: A new high-speed domino circuit, called HS-Domino is developed. HS-Domino resolves the trade-off between performance and noise margins in conventional CD-Domino logic while dissipating low dynamic power with minimal area overhead. A dual-threshold (MTCMOS) implementation of HS-Domino and DDCVS logic is also devised. This implementation achieves low leakage values during standby, while maintaining high performance and low dynamic power during the active mode.

Fast and efficient parametric modeling of contact-to-substrate coupling

Abstract: This paper presents two rapid and yet accurate modeling methods for substrate coupling between a device contact and a substrate backplane. We discuss effects of physical parameters and geometrical characteristics of the contact and the substrate on the proposed models. We also derive model expressions for extraction of circuit-model elements of the substrate. Both methods are efficient for speed, memory usage, and adaptable to computer-aided design (CAD) tools for optimization tasks. The accuracy of both methods, the parametric modeling method and the microstrip line approximation method, is validated by comparing with the rigorous simulation data obtained from IE3D. Using the new models, we record a much higher speedup factor and extremely lower memory requirements compared to other published methods. The modeling methods are extended to two-layer structures and the models are applied to spiral inductors for verification purposes. In our research, we have validated the models over a wide range of frequencies up to 20 GHz.

Low-power design of decimation filters for a digital IF receiver

Abstract: This paper presents low-power design techniques at the architectural level for design of decimation filters in a digital IF receiver for wide-area wireless data networks. A multimode decimation filter design implementing both Mobitex and Ardis networks is described. The power is reduced by a factor of 1422 and the area reduced by a factor of 7.85 compared to an optimized single-mode two-stage design. A new multistage decimation filter design tool is also presented, which compares alternative architectures on figures of merit which the low-power designer can map into technology-dependent area and power costs.

Dynamic current mode logic (DyCML), a new low-power high-performance logic family

Abstract: This paper presents a new logic style DyCML for low-power high-performance VLSI applications. The new logic family combines the speed, low supply voltage and noise immunity advantages of MCML circuits while achieving the low standby current and design simplicity features of dynamic circuits. Simulation results show that DyCML circuits are superior to CMOS and DCVS logic styles in terms of power and delay. A 16 bit DyCML Carry Look Ahead Adder (CLA) fabricated in 0.6 /spl mu/m achieves a delay of 1.1 ns while dissipating 21.2 mW at 400 MHz.

Effect of technology scaling on digital CMOS logic styles

Abstract: In this paper, the main challenges of technology scaling are reviewed in depth. Five popular logic families, namely, conventional CMOS, CPL, Domino, DCVS and MCML are represented highlighting their advantages and drawbacks. The behavior of each logic style in deep submicron technologies is analyzed and predicted for future generations. To verify the qualitative analysis, simulations were performed on the basic logic gates, full adder and a 16-bit carry look ahead adder. The circuits were implemented in 0.8, 0.6, 0.35 and 0.25 /spl mu/m CMOS technologies.

A fully-integrated low phase-noise nested-loop PLL for frequency synthesis

Abstract: It is greatly beneficial to integrate the VCO. An efficient way to accomplish that is through the help of wide-bandwidth PLLs. This paper presents a simple nested-loop PLL architecture that achieves very wide BW while maintaining the required frequency resolution and spur rejection. The wide-BW loop, including the loop filter, is integrated on a single chip in a 25 GHz bipolar process. The PLL achieves a phase-noise of -100 dBc/Hz at 10 kHz offset from 1 GHz and consumes 9.9 mA from a 3.3 V supply.

An efficient and accurate model for RF/microwave spiral inductors using microstrip lines theory

Abstract: This paper presents a rapid and efficient modeling method, based on the microstrip lines theory, for the coupling between a device contact and the substrate backplane. We derive simple closed-form formulas to model spiral inductors as important substrate-noise sources in mixed-signal systems. The model has been verified via IE3D simulations up to 35 GHz, and is adaptable to CAD tools. We demonstrate that the accuracy of the proposed model is better than 8%.

Simulation of Temperature Dependence of Microwave Noise in Metal-Oxide-Semiconductor Field-Effect Transistors

Abstract: We present results of a two-demensional (2D) numerical simulation of high-frequency noise in a short-channel metal-oxide-semiconductor field-effect transistors (MOSFET). Conventionally this noise in MOSFETs is treated as a thermal noise with a rather slow temperature dependence of the noise spectra. On contrary, the results obtained indicate that this dependence is more of an exponential kind, typical for a shot noise. Shot noise is conventionally related to a forward biased p-n junction where the current is mostly due to diffusion in the quasi-neutral region. We therefore speculate that most likely in short channel MOSFETs most of the high-frequency noise is produced not in the cut-off region of the channel but near the source side of the channel where diffusion current component is dominant.

An efficient technique for substrate coupling parasitic extraction with application to RF/microwave spiral inductors

Abstract: This paper presents an efficient modeling method based on the microstrip lines theory for the coupling between a substrate backplane and a device contact. We derive simple closed-form formulas for rapid extraction of substrate parasitics. We use these formulas to model spiral inductors as important substrate-noise sources in mixed-signal systems. The proposed model is verified for the frequencies up to 35 GHz, and is easily adaptable to CAD tools.

Low power high speed analog-to-digital converter for wireless communications

Abstract: A new ADC architecture is devised. This architecture is memory based, in which the last sample is used to predict the current one, resulting in both power dissipation and energy reduction. The low power dissipation is a vital factor when we consider the chip reliability and integrity. The low energy consumption is a critical factor when we deal with battery operated devices like PCSs. This technique may also be used to extend the attainable flash converter resolution by pre-calculating the most significant bits.

A semi-analytical quasi-static approach for substrate coupling modeling in VLSI circuits

Abstract: This paper presents a method for modeling substrate coupling. It also derives closed-form expressions for evaluating coupling elements between two device contacts. Using these expressions, we develop a method for extracting substrate coupling elements in a multi-contact structure. A comparison between our technique and another from the literature for a multi-contact scenario demonstrates the efficiency of our technique.

Simulation of internal distribution of microwave noise sources in a short-channel nMOSFET

Abstract: High frequency excess noise in short-channel MOSFETs is discussed from the point of view of internal device characteristics, such as noise source density and current densities. It is demonstrated that the current density component perpendicular to the interface produces a major portion of the high frequency (diffusion) noise in short-channel MOSFETs.