Showing papers by "Mohammed Ismail published in 2001"

A CMOS fully balanced differential difference amplifier and its applications

Abstract: We present the fully balanced version of the differential difference amplifier (DDA) as an essential building block for implementing fully differential architectures of analog CMOS integrated circuits (ICs). It is demonstrated that the fully balanced differential difference amplifier (FBDDA) provides the solution for systematically developing fully differential versions of any single-ended op-amp based circuit. It is also shown that, unlike the DDA, the FBDDA exhibits a wide input range without demanding complex circuitry. A low-power class AB CMOS realization of the proposed circuit has been designed and fabricated in a 1.2 /spl mu/m technology. All proposed design techniques and circuits were experimentally verified.

CMOS VHF/RF CCO based on active inductors

Abstract: CMOS VHF/RF CCO based on active inductors A novel CMOS current controlled oscillator (CCO) is proposed. Based on the current-reused active inductors, a differential oscillator has been designed and fabricated. Measurement results show that it has very wide tuning-range and reasonable phase-noise performance.

RF CMOS Power Amplifiers: Theory, Design and Implementation

Abstract: List of Figures. List of Tables. Preface. 1. Introduction. 2. Power Amplifier Concepts and Challenges. 3. A 900MHZ Class E CMOS PA. 4. CMOS PA for Bluetooth. 5. A Complete Bluetooth PA Solution. 6. Conclusion. Index.

A CMOS Norton amplifier-based digitally controlled VGA for low-power wireless applications

Abstract: A CMOS variable-gain amplifier (VGA) for use in the baseband section of integrated wireless receivers is presented. The VGA circuit is based on a new CMOS realization of the Norton transresistance amplifier. The proposed CMOS realization operates from a 3-V supply voltage with rail-to-rail swing and class AB input and output stages. The standby current of the class AB stages employed can be accurately controlled, leading to a low power consumption, nonslew-rate-limited response. The VGA circuit provides a precise process-independent gain control range of 30 dB with 1-dB gain step. The circuit uses current division techniques to provide an area-efficient 6-bit digital offset trimming capability. Experimental results from a test chip fabricated through MOSIS are provided.

Compact low voltage four quadrant CMOS current multiplier

Abstract: A new compact low voltage four quadrant current mode CMOS multiplier is presented. Post layout simulation in a CMOS 0.5 mum technology shows a linearity error lower than 0.9% for signal swings up t ...

A new generation of global wireless compatibility

Abstract: The expanding growth of wireless communications has led to the proliferation of different standards. The highly competitive market demands low-cost, low-power, and small form-factor devices. This calls for the development of a single-chip, third-generation (3G) receiver capable of adapting to the various communications standards in a low-cost CMOS technology. However, fully integrated receiver architectures require the elimination of discrete high-Q image rejection and IF filters. Thus, the received signal is down-converted to baseband without channel filtering, which most frequently results in the presence of strong adjacent channel blockers along with the desired signal. Therefore, it is required from the baseband filter design to exhibit a high-dynamic range, a programmable bandwidth to accommodate different standards, precise tuning to select the desired channel within a standard, low power, and a small chip area. This article discusses the 3G wireless systems with a focus on the design of a reconfigurable baseband chain that precedes the ADC of a multistandard fully integrated wireless receiver. The baseband chain is adapted to accommodate the GSM, IS-95, and wideband CDMA wireless standards.

Describing functions and oscillators

Abstract: In this article the "Describing Function" technique is applied to the analysis and design of oscillators. It is shown that, with some simplifications of the expressions involved in the analysis, this technique allows one not only to quantify the amplitude but also to determine the degree of distortion of the generated sinusoidal signal. The advantage of the describing function is that it allows the inclusion of the nonlinear behavior of a system while maintaining the simplicity often associated with the linear system analysis. This will be demonstrated through an example presenting the analysis and design of a sinusoidal oscillator in the frequency domain. The method as such allows formulation of closed-form expressions for the amplitude and distortion levels in much the same way classical linear techniques are used.

Data converters for wireless standards

Abstract: List of Figures. List of Tables. Preface. 1. Introduction. 2. Overview of Wireless Receiver Architectures. 3. Low Power ADC Design. 4. Prototype Design: ADC for WLAN(DSSS)/WCDMA. 5. Design Considerations of Low Voltage ADCS. 6. ADC for Bluetooth/WLAN(FHSS)/HOMERF. 7. High-Resolution DAC Design Techniques. 8. Control DAC for 3G (UMTS) Transceivers. 9. Conclusion. Index.

A low-noise fast-settling PLL with extended loop bandwidth enhancement by new adaptation technique

Abstract: A new adaptation scheme for low noise and fast settling phase locked loops (PLLs) is presented. Extended loop bandwidth enhancement is achieved by the adaptive control on the reference frequency and frequency divide ratio. It enables the loop bandwidth in the speed-up mode to greatly exceed the limit of approximately 1/10 of the channel spacing in the integer frequency synthesizer. Based on the proposed adaptation scheme, a 450 MHz frequency synthesizer with a 200 kHz channel spacing is implemented in 0.5 /spl mu/m CMOS process. In the speed-up mode, the loop bandwidth is enhanced by 16 times, resulting in a fast settling time of 260 /spl mu/s to within 20 kHz for a 72 MHz frequency step by simulation.

Robust design and yield enhancement of low-voltage CMOS analog integrated circuits

Abstract: Basic CMOS low-voltage analog cells are introduced and used in the design of low-voltage CMOS multipliers. A statistical design flow for enhancing the parametric functional yield of these low-voltage circuits, with the goal of achieving a robust performance, is described. The design flow is based on using the response surface methodology (RSM) and design of experiments (DOE) techniques as statistical VLSI design techniques together with the statistical MOS (SMOS) model. Offset and nonlinearity performances are statistically examined. The response surfaces show the trade-off between area and functional yield. Using these surface contours, the designer will be able to estimate the functional yield of the circuits before fabrication. The contours are also used in the statistical optimization of device sizes as they provide information regarding which transistor aspect ratios are to be altered to achieve a better functional yield.

CMOS limiters with RSSIs for Bluetooth receivers

Abstract: Two different low power CMOS limiters with received signal strength indicators (RSSIs) are presented. RSSIs are implemented using piecewise linear logarithmic amplifiers. The limiters and RSSIs are designed for Bluetooth receivers at 3 MHz IF using 0.35 /spl mu/m and 0.5 /spl mu/m CMOS technologies. Input dynamic range of the limiters is more than 65 dB, and RSSI error is within /spl plusmn/3 dB which satisfies Bluetooth requirements. The limiters with RSSIs consumes 1.2 mA and 1.6 mA with 2.7 V power supply.

A fully integrated dual-mode frequency synthesizer for GSM and Wideband CDMA in 0.5/spl mu/m CMOS

Abstract: A fully integrated dual-mode frequency synthesizer for GSM and Wideband CDMA (WCDMA) is presented. The synthesizer is designed to maximize hardware sharing between the two modes by applying fractional frequency synthesis to GSM mode and integer frequency synthesis to WCDMA mode. The shared components include phase frequency detector (PFD), charge pump (CP), loop filter, integer frequency divider and VCO, which is 70% of the entire synthesizer in term of die area. A high-speed low power dual modulus prescaler is proposed to operate up to 2.1GHz at 3.3V supply voltage with 11.6mW power consumption by simulation. A dual mode VCO is also proposed for the enhanced tuning range with an accumulation mode NMOS varactor for band-to-band tuning and a p/sup +/n junction varactor for in-band tuning. The simulation result shows that the synthesizer phase noise is -112dBc/Hz at 600kHz offset frequency for WCDMA mode and -117 dBc/Hz for GSM mode.

Design techniques for improving intrinsic accuracy of resistor string DACs

Abstract: This paper discusses design techniques for random and gradient errors compensation in resistor string digital-to-analog converters (DACs). By properly constructing the resistor string, the intrinsic accuracy of the whole DAC can be effectively improved without trimming, calibration or dynamic averaging. A design example is given and simulation results show that the proposed techniques can increase the accuracy of DAC by up to 2 bits with less than 25% area increase.

Inductorless CMOS RF bandpass filter

Abstract: The design and experimental results of a novel CMOS RF filter are presented, Employing a pair of current-reused active inductors. a differential second-order bandpass filter working at 900 M Hz wit ...

A front-end receiver sigma-delta modulator

Abstract: The present invention relates to a sigma-delta modulator, which is operative in different standard modes for processing communication signals of different communication standards. The modulator comprises a 1-bit quantizer and a multi-bit quantizer, and a switching mechanism for switching between said quantizers in dependence of the standard mode. The invention further relates to an A/D converter comprising such a modulator, a multi-standard RF receiver comprising such an A/D converter, and a method for signal processing of communication signals of different communication standards.

Statistical Design of a 10 bit Current Division Network

Abstract: The statistical design of the 10 bit current division network is presented in this paper. The quantitative measure of the effect of mismatch between the transistors in the circuit is provided. Optimization of transistor W and L values, and yield enhancement are demonstrated. The circuit is fabricated through the MOSIS 2\ \mu {\rm m} process using MOS transistor Level-3 model parameters. Experimental results are included in the paper.

Design and power optimization of high-speed pipeline ADC for wideband CDMA applications

Abstract: This paper presents a 7-bit 64 MS/s pipeline A/D converter suitable for wideband CDMA applications Targeting at achieving low power dissipation at high speed, techniques such as digital correction and optimal scaling of capacitor value have been employed Switched-Opamp technique is used to further reduce power consumption This ADC is implemented in 05 μm standard CMOS process It operates from a single 3 V supply, and dissipates only 31 mW at 64 MS/s

A High-Speed Low-Power Divide-by-15/16 Dual Modulus Prescaler in 0.6 μm CMOS

Abstract: A new high-speed low-power dual modulus prescaler (DMP) topology is proposed. In this DMP, the synchronous part is designed as a divide-by-3/4 divider using a state-selection scheme. Compared with the conventional divide-by-4/5 divider, it has a higher speed by eliminating the NAND-gate introduced critical path delay, as well as a lower power consumption by minimizing the number of full-speed D-type flip-flops (DFF's) required. Based on this topology, a divide-by-15/16 DMP is implemented in the 0.6 μm standard CMOS process. Simulation result shows that a maximum operating frequency of 2.15 GHz is obtained at 3.3 V supply with a power consumption of 11.6 mW. The circuit can operate above 3 GHz with 5 V supply and down to 1.5 V supply voltage with 570 MHz input frequency.

Dual-loop cross-coupled feedback amplifier for low-IF integrated receiver architecture

Abstract: This paper presents a combined LNA and mixer suitable for low-IF architecture. This combination gives an improved linearity without consuming high bias-current. Simulations show an improvement in IIP/sub 3/ by a factor of 3-7.4 dB, depending on the frequency, at a power consumption and a noise figure equivalent to that of the traditional configuration. The circuit presented here is a wideband circuit, which might be suitable for area-efficient multi-band receivers.

A digitally controlled CMOS RF power amplifier

Abstract: This paper presents the design, and implementation of an RF power amplifier in a standard 0.35 /spl mu/m CMOS technology. The amplifier is capable of delivering 16.5 dBm of output power at 1.85 GHz using a 3.3 V supply with an overall measured power added efficiency (PAE) of 30%. The power amplifier employs a class AB output stage, which represents a compromise between efficiency and linearity. Measurement results of the fabricated chip are included.

Robust design of low power CMOS analogue integrated circuits

Abstract: As feature sizes move into the deep submicron ranges and power supply voltages are reduced, the effect of both device mismatch and inter-die process variations on the performance and reliability of analogue integrated circuits is magnified. The statistical MOS (SMOS) model accounts for both inter-die and intra-die variations. A low power analogue CMOS square-law cell, and a new transconductor and multiplier using this cell as the main building block, are presented in the paper. The paper focuses on the robust design of the transconductor and multiplier circuits. The circuits operate in the saturation region with fully balanced input signals. Initial circuit simulation results are given. Response surface methodology and design of experiment techniques were used as statistical VLSI design techniques combined with the SMOS model. Device size optimisation and yield enhancement are demonstrated.

Behavioral modeling of rf VCO circuit with MEMS LC resonator

Abstract: In this work, a behavioral Modeling of RF VCO circuit which has a tank designed by Microelectromechanical system (MEMS) technology is presented emphasizing robust design that can obtain the parametric variable of the suspended spiral inductor and the MEMS tunable capacitor to high performance and reliable design of the VCO circuit. The MEMS spiral inductor has a low phase noise effect on the VCO output, and the MEMS tunable capacitance has very high quality factor with enabling 20% change of oscillation frequency. The designed monolithic RF VCO circuit and the high-Q MEMS inductor and tunable capacitor are modeled using specter-s simulator in the CADENCE design framework and (Verilog-A) behavioral simulator. Complete monolithic fabrication of RF VCO with high-Q MEMS devices using standard CMOS process (MOSIS, AMI 1.2 micrometer).

Statistical Design of the Four-MOSFET Structure

Abstract: The statistical design of the four-MOSFET structure is presented in this paper. The quantitative measure of the effect of mismatch between the four transistors on nonlinearity and offset current is provided through contours. Statistical optimization of the transistor W and L values is demonstrated. The four-MOSFET structure was fabricated through the MOSIS 2 μm process using MOS transistor Level-3 model parameters. Experimental results are included in the paper.