VMOS is a new v-groove n-channel MOS logic structure well suited for 5-V high-speed random logic. Compared to a typical gold-doped TTL medium-scale integrated (MSI) circuit, an experimental pin for pin equivalent VMOS circuit is 20 percent faster, four times smaller in area, and six times lower in power dissipation. On-chip VMOS delays are in the 2-3 ns range; off-chip drive capability exceeds 50 MHz with 6 TTL unit loads.

VMOS: high speed TTL compatible MOS logic

Schottky I/SUP 2/L uses the principles of integrated injection logic (I/SUP 2/L/MTL) and the properties of ion implantation to obtain improved performance at the same densities as conventional I/SUP 2/L. Schottky diodes are formed in the multicollectors of the switching transistor and reduce the signal swing, thus improving the power delay efficiency. An increase in the intrinsic speed limit is also feasible. The Schottky I/SUP 2/L structure and characteristics are described and contrasted with conventional I/SUP 2/L. A model which is useful for its design is discussed. Integrated test structures which provide direct comparison between conventional and Schottky I/SUP 2/L performance have been fabricated. The experimental results demonstrate a factor of 2 improvement in power-delay efficiency of Schottky I/SUP 2/L over conventional I/SUP 2/L.

Schottky I/sup 2/L

A high performance, second generation I/SUP 2/L/MTL gate for digital LSI applications with TTL compatibility has successfully been designed, characterized, and demonstrated fully functional over a wide current range and the military temperature range of -55 to 125/spl deg/C. Performance is measured using an in-line five-collector gate having one end injector. The gate performed with the following characteristics at 100 /spl mu/A injector current: /spl beta//SUB U//SUP eff//spl ges/4 for all collectors at 25/spl deg/C and /spl ges/2.5 at -55/spl deg/C, /spl alpha//SUB rec///spl alpha//SUB F//spl cong/0.58 and /spl tau/~/SUB d/=18-20 ns from -55 to 125/spl deg/C, and a speed-power product of 1.4 pJ at 25/spl deg/C. At low injector currents, a constant speed-power product of 0.36 pJ at 25/spl deg/ was obtained.

Second generation I/sup 2/L/MTL: a 20 ns process/structure

Using a simple channel implantation step, the choice of the threshold voltage determines speed and power. Illustrations are given by the example of a 3-input NOR-gate with 1/spl times/5-/spl mu/m/SUP 2/ channel geometry for the switching transistors. A design with dual threshold voltages allowing the optimization of power consumption while keeping subnanosecond propagation delay times is presented and applied to a speed- and power-optimized dual-type MESFET NOR-gate. Examples are presented of experimental d.c. characteristics measured on fabricated samples exhibiting an average power consumption of 150 /spl mu/W. A propagation delay time of 0.8 ns is deduced for a fan-out of 3. This performance is discussed in conjunction with a set of parameters including geometry, technological reproducibility, and circuit design requirements. It appears that geometries of about 1 /spl mu/m lead to the best compromise for fast switching and optimized LSI organization.

A subnanosecond integrated switching circuit with MESFET's for LSI

This paper reports the design, fabrication, and characterization of a diffusion self-aligned enhancement depletion (DSA-ED) MOS IC. It is shown that using DSA structure, a short channel MOST with effective submicron channel length can be realized even by standard photolithographic techniques. High-speed characteristics of a DSA MOST, high gain factors, and small drain junction capacitance are described. The advantage of an ED configuration is discussed. To evaluate the basic performance of the gate, 19-stage ring oscillators with various device sizes have been developed. In the ring oscillator design, the high gain factors of the DSA MOST are fully utilized to minimize the device size and upgrade the performance and packing density. A propagation delay time of 0.65 ns, a power dissipation of 0.15 mW, a power delay product of 0.10 pJ at the supply voltage 2 V, and a packing density of 510 gate/mm/SUP 2/ have been obtained by the single-level metal interconnections of 7 /spl mu/m details. A 4-bit arithmetic logic unit (ALU) has been developed with the same design principle and device size to obtain the 2.9 ns/gate, 0.71 mW/gate performance at the supply voltage of 5 V and 141 gates/mm/SUP 2/ packing density.

A high-speed logic LSI using diffusion self-aligned enhancement depletion MOS IC

Integrated injection logic (I/SUP 2/L) or merged transistor logic (MTL) incorporating lateral p-n-p transistors as current sources and multicollector n-p-n transistors as invertors, are discussed. Speed-power products of 0.13 pJ per gate have been measured in a five-stage closed-loop invertor chain, and packing densities of 400 gates/mm/SUP 2/ have been achieved. A layout comparison with MOS logic is presented. A possible way of producing faster circuits is proposed.

Integrated injection logic-present and future

Integrated injection logic found to afford lateral PNP transistors as current sources and multicollector NPN transistors as inverters will be discussed. Packing densities of 400 gates/mm2and speed power products of 0.13 pJ have been realized. Comparison with MOS logic will be offered.

https://ieeexplore.ieee.org/iel6/8288/25920/01155334.pdf

Invited: Integrated injection logic - A new approach to LSI

A method of design is presented for logical circuits, starting from worst-case considerations. The method represents an approach to dc optimization. Special attention is paid to temperature and tolerance problems in monolithic integrated circuits. In the worst-case design procedure outlined, the requirements for obtaining a properly functioning circuit are taken as the point of departure. This results in a whole field of possible circuits from which?depending on further specifications?it is comparatively easy to find special solutions. Three examples of worst-case calculations are developed?one for a transistor-transistor logic circuit, one for a diode-transistor logic circuit, and finally, one for a new type of circuit, termed emitter-follower transistor logic.

Worst-Case Considerations in Designing Logical Circuits

It is shown that the propagation delay time of i.i.l. at low current levels is given by tr/2 if tf < tr, where tf is the fall time and tr the rise time at an i.i.l. input node. An expression for tr and tf can easily be found.

N.C. De Troye

Papers

Integrated injection logic-present and future

Invited: Integrated injection logic - A new approach to LSI

Worst-Case Considerations in Designing Logical Circuits

Propagation delay time of i.i.l. at low current levels