Nandar Su

TL;DR: In this article, a chip level stack module is achieved by stacking two thin dies of different sizes and thickness together using flip chip technology with micro bump interconnects, and the assembled Si die stacked modules are subjected to JEDEC package level reliability tests in terms of temperature cycle test (TC), high temperature storage test (HTS), moisture sensitivity test level 1 (MST L1) and MST L3, and unbiased High accelerated stress test (uHAST).

TL;DR: In this article, two embedded micro wafer level packages (EMWLP) with laterally placed and vertically stacked thin dies are designed and developed, illustrated as progressive miniaturization driver for multi-chip EMWLP.

TL;DR: In this article, the development of ultra fine pitch and high density solder microbumps for advanced 3D stacking technologies is discussed and the assembly of the Si chip and the Si carrier is conducted with the FC150 flip chip bonder at different temperatures, times, and pressures and the optimized bonding conditions are obtained.

TL;DR: In this paper, a liquid cooling solution has been reported for 3D package in PoP format, where a high heat dissipating chip is mounted on a silicon carrier, which has copper through-silicon via for electrical interconnection and throughsilicon hollow via for fluidic circulation.

TL;DR: In this paper, a narrowband low-loss 77-GHz band pass filter on EMWLP platform is demonstrated in a 5.5 GHz band filter targeted for WLAN applications.