Srinivasa Rao Vempati

TL;DR: In this article, the TSV interposer was used to provide high wiring density interconnection, to minimize CTE mismatch to the Cu/low-k chip that is vulnerable to thermal-mechanical stress, and to improve electrical performance due to shorter interconnection from the chip to the substrate.

TL;DR: In this article, a chip level stack module is achieved by stacking two thin dies of different sizes and thickness together using flip chip technology with micro bump interconnects, and the assembled Si die stacked modules are subjected to JEDEC package level reliability tests in terms of temperature cycle test (TC), high temperature storage test (HTS), moisture sensitivity test level 1 (MST L1) and MST L3, and unbiased High accelerated stress test (uHAST).

TL;DR: In this paper, a series of parametric studies are performed by changing the die thickness, die pitch distance and top mold chaste compression velocity to predict the die shift during compression molding.

TL;DR: In this paper, a die package is presented, which includes a second die arranged above a first die, the first die comprising an interconnect region on a surface facing the second die, wherein the second dies is arranged laterally next to the interconnect regions of the first dies, and a package material formed partially around the first package-internal free-standing interconnect structure such that a connecting portion remains uncovered.

TL;DR: In this paper, a narrowband low-loss 77-GHz band pass filter on EMWLP platform is demonstrated in a 5.5 GHz band filter targeted for WLAN applications.