The high-performance room-temperature-operating Si single-electron transistors (SETs) were devised in the form of the multiple quantum-dot (MQD) multiple tunnel junction (MTJ) system. The key device architecture of the Si MQD MTJ system was self-formed along the volumetrically undulated [110] Si nanowire that was fabricated by isotropic wet etching and subsequent oxidation of the e-beam-lithographically patterned [110] Si nanowire. The strong subband modulation in the volumetrically undulated [110] Si nanowire could create both the large quantum level spacings and the high tunnel barriers in the Si MQD MTJ system. Such a device scheme can not only decrease the cotunneling effect, but also reduce the effective electron temperature. These eventually led to the energetic stability for both the Coulomb blockade and the negative differential conductance characteristics at room temperature. The results suggest that the present device scheme (i.e., [110] Si MQD MTJ) holds great promise for the room-temperature demonstration of the high-performance Si SETs.

/pdf/reduced-electron-temperature-in-silicon-multi-quantum-dot-3b7insak.pdf

Reduced Electron Temperature in Silicon Multi-Quantum-Dot Single-Electron Tunneling Devices

The spin of an electron confined in semiconductor quantum dots is currently a promising candidate for quantum bit (qubit) implementations. Taking advantage of existing CMOS integration technologies, such devices can offer a platform for large scale quantum computation. However, a quantum mechanical framework bridging a device's physical design and operational parameters to the qubit energy space is lacking. Furthermore, the spin to charge coupling introduced by intrinsic or induced Spin-Orbit-Interaction (SOI) exposes the qubits to charge noise compromising their coherence properties and inducing quantum gate errors. We present here a co-modelling framework for double quantum dot (DQD) devices and their charge noise environment. We use a combination of an electrostatic potential solver, full configuration interaction quantum mechanical methods and two-level-fluctuator models to study the quantum gate performance in realistic device designs and operation conditions. We utilize the developed models together alongside the single electron solutions of the quantum dots to simulate one- and two- qubit gates in the presence of charge noise. We find an inverse correlation between quantum gate errors and quantum dot confinement frequencies. We calculate X-gate fidelities>97% in the simulated Si-MOS devices at a typical TLF densities. We also find that exchange driven two-qubit SWAP gates show higher sensitivity to charge noise with fidelities down to 91% in the presence of the same density of TLFs. We further investigate the one- and two- qubit gate fidelities at different TLF densities. We find that given the small size of the quantum dots, sensitivity of a quantum gate to the distance between the noise sources and the quantum dot creates a strong variability in the quantum gate fidelities which can compromise the device yields in scaled qubit technologies.

Modeling semiconductor spin qubits and their charge noise environment for quantum gate fidelity estimation

The single electron transistor (SET) is a nanoscale switching device with a simple equivalent circuit. It can work very fast as it is based on the tunneling of single electrons. Its nanostructure contains a quantum dot island whose material impacts on the device operation. Carbon allotropes such as fullerene (C60), carbon nanotubes (CNTs) and graphene nanoscrolls (GNSs) can be utilized as the quantum dot island in SETs. In this study, multiple quantum dot islands such as GNS-CNT and GNS-C60 are utilized in SET devices. The currents of two counterpart devices are modeled and analyzed. The impacts of important parameters such as temperature and applied gate voltage on the current of two SETs are investigated using proposed mathematical models. Moreover, the impacts of CNT length, fullerene diameter, GNS length, and GNS spiral length and number of turns on the SET’s current are explored. Additionally, the Coulomb blockade ranges (CB) of the two SETs are compared. The results reveal that the GNS-CNT SET has a lower Coulomb blockade range and a higher current than the GNS-C60 SET. Their charge stability diagrams indicate that the GNS-CNT SET has smaller Coulomb diamond areas, zero-current regions, and zero-conductance regions than the GNS-C60 SET.

/pdf/schemes-for-single-electron-transistor-based-on-double-112ou5sk.pdf

Schemes for Single Electron Transistor Based on Double Quantum Dot Islands Utilizing a Graphene Nanoscroll, Carbon Nanotube and Fullerene

In this work we explore the fabrication and exper-imental characterization of multi-gate FD-SOI devices that can operate both as single electron transistors (SETs) and MOSFETs. FD-SOI SET operation is achieved with electrostatically induced tunneling barriers controllable by two barrier gates ( <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{B}_{L}$</tex> and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{B}_{R}$</tex> ) and a front gate (FG), the device operation being additionally tunable by a bottom gate (BG). Coulomb blockade current measurements at 10 mK and 4 K demonstrate the possibility of a dynamic transition from a FD-SOI MOSFET and SET operation, making this technology suitable for hybrid SET-MOSFET low power cryogenic circuits for quantum information processing. Room temperature back-gate characterization has been performed on ultra-thin film devices proving the effective reduction of charge noise for a specific bias configuration. This experimental work is a step forward towards low noise planar FD-SOI quantum dots based devices with tunable electrostatic control. 

Multi-Gate FD-SOI Single Electron Transistor for hybrid SET-MOSFET quantum computing

This study addresses the complementary metal-oxide-semiconductor-compatible fabrication of vertically stacked Si/SiO2/Si nanopillars (NPs) with embedded Si nanodots (NDs) as key functional elements of a quantum-dot-based, gate-all-around single-electron transistor (SET) operating at room temperature. The main geometrical parameters of the NPs and NDs were deduced from SET device simulations using the nextnano++ program package. The basic concept for single silicon ND formation within a confined oxide volume was deduced from Monte-Carlo simulations of ion-beam mixing and SiO x phase separation. A process flow was developed and experimentally implemented by combining bottom-up (Si ND self-assembly) and top-down (ion-beam mixing, electron-beam lithography, reactive ion etching) technologies, fully satisfying process requirements of future 3D device architectures. The theoretically predicted self-assembly of a single Si ND via phase separation within a confined SiO x disc of <500 nm3 volume was experimentally validated. This work describes in detail the optimization of conditions required for NP/ND formation, such as the oxide thickness, energy and fluence of ion-beam mixing, thermal budget for phase separation and parameters of reactive ion beam etching. Low-temperature plasma oxidation was used to further reduce NP diameter and for gate oxide fabrication whilst preserving the pre-existing NDs. The influence of critical dimension variability on the SET functionality and options to reduce such deviations are discussed. We finally demonstrate the reliable formation of Si quantum dots with diameters of less than 3 nm in the oxide layer of a stacked Si/SiO2/Si NP of 10 nm diameter, with tunnelling distances of about 1 nm between the Si ND and the neighboured Si regions forming drain and source of the SET.

https://iopscience.iop.org/article/10.1088/1361-6641/acbe5d/pdf

CMOS-compatible manufacturability of sub-15 nm Si/SiO2/Si nanopillars containing single Si nanodots for single electron transistor applications

Recent advances demonstrated the feasibility of realizing spin-based quantum computation in Silicon. To make further progress towards a large-scale implementation of spin-based quantum device technologies, a reliable fabrication process with good yield and device uniformity is a crucial requirement. We address this challenge by integrating a prototype spin qubit device in a 300 mm process, using state-of-the-art, CMOS-compatible process steps. We demonstrate well-formed single-electron transistors with a feature size of 50 nm, individual electron controllability and show multi-gate control uniformity from room-down to low-temperature. Dots with charging energies of 1–2 meV and sizes of around 46 nm are estimated, in excellent agreement with design geometry. The noise power spectrum reveals 1/f noise with an amplitude of $2~\mu $ eV at 1 Hz. This successful integration enables further exploration of reproducible Silicon-based spin qubit devices and opens paths for systematic investigation of the performance and scalability of future spin-based qubit devices.

Nard Dumoulin Stuyck

Papers

An Integrated Silicon MOS Single-Electron Transistor Charge Sensor for Spin-Based Quantum Information Processing