Nicolas Borrel

TL;DR: The experimental evaluation of a complete BBICS architecture, designed to simultaneously monitor PMOS and NMOS transistors, under Photoelectric Laser Stimulation (PLS) is reported, providing the first experimental proof of the efficiency of BBICS in laser fault injection detection attempts.

TL;DR: This paper reports similar experiments carried out using shorter laser pulses (30 ps duration instead of 50 ns) and proposes an upgrade of the simulation model they used to take into account laser pulses in the picosecond range, which confirmed the validity of the bit-set/bit-reset fault model over thebit-flip one.

TL;DR: The design of a CMOS 40 nm D Flip-Flop cell is presented and the laser fault sensitivity mapping both with experiments and simulation results and an upgrade of the simulation model used to take into account laser pulse durations in the picosecond range on a logic gate composed of a large number of transistors for a recent CMOS technology.

TL;DR: Measurements of the photoelectric currents induced by a pulsed-laser on an NMOS transistor in triple-well Psubstrate/DeepNwell/Pwell structure dedicated to low power body biasing techniques are presented and an electrical model is proposed that makes it possible to simulate the effects induced by photoelectric laser stimulation.

TL;DR: In this article, the photoelectric currents induced by a pulsed laser on a triple-well Psubstrate/DeepNwell/Pwell structure dedicated to low power body biasing techniques were analyzed.