Side-channel attacks on mobile devices have gained increasing attention since their introduction in 2007. While traditional side-channel attacks, such as power analysis attacks and electromagnetic analysis attacks, required physical presence of the attacker as well as expensive equipment, an (unprivileged) application is all it takes to exploit the leaking information on modern mobile devices. Given the vast amount of sensitive information that are stored on smartphones, the ramifications of side-channel attacks affect both the security and privacy of users and their devices. In this paper, we propose a new categorization system for side-channel attacks, which is necessary as side-channel attacks have evolved significantly since their scientific investigations during the smart card era in the 1990s. Our proposed classification system allows to analyze side-channel attacks systematically, and facilitates the development of novel countermeasures. Besides this new categorization system, the extensive survey of existing attacks and attack strategies provides valuable insights into the evolving field of side-channel attacks, especially when focusing on mobile devices. We conclude by discussing open issues and challenges in this context and outline possible future research directions.

/pdf/systematic-classification-of-side-channel-attacks-a-case-4b7elipt9q.pdf

Systematic Classification of Side-Channel Attacks: A Case Study for Mobile Devices

Side-channel attacks on mobile devices have gained increasing attention since their introduction in 2007. While traditional side-channel attacks, such as power analysis attacks and electromagnetic analysis attacks, required physical presence of the attacker as well as expensive equipment, an (unprivileged) application is all it takes to exploit the leaking information on modern mobile devices. Given the vast amount of sensitive information that are stored on smartphones, the ramifications of side-channel attacks affect both the security and privacy of users and their devices. 
In this paper, we propose a new categorization system for side-channel attacks, which is necessary as side-channel attacks have evolved significantly since their scientific investigations during the smart card era in the 1990s. Our proposed classification system allows to analyze side-channel attacks systematically, and facilitates the development of novel countermeasures. Besides this new categorization system, the extensive survey of existing attacks and attack strategies provides valuable insights into the evolving field of side-channel attacks, especially when focusing on mobile devices. We conclude by discussing open issues and challenges in this context and outline possible future research directions.

Physically Unclonable Functions (PUFs) are introduced to remedy the shortcomings of traditional methods of secure key storage and random key generation on Integrated Circuits (ICs). Due to their effective and low-cost implementations, intrinsic PUFs are popular PUF instances employed to improve the security of different applications on reconfigurable hardware. In this work we introduce a novel laser fault injection attack on intrinsic PUFs by manipulating the configuration of logic cells in a programable logic device. We present two fault attack scenarios, where not only the effectiveness of modeling attacks can be dramatically increased, but also the entropy of the targeted PUF responses are drastically decreased. In both cases, we conduct detailed theoretical analyses by considering XOR arbiter PUFs and RO PUFs as the examples of PUF-based authenticators and PUF-based random key generators, respectively. Finally we present our experimental results based on conducting laser fault injection on real PUFs, implemented on a common complex programmable logic device manufactured in 180 nm technology.

Laser Fault Attack on Physically Unclonable Functions

Side-channel analysis and fault-injection attacks are known as major threats to any cryptographic implementation. Hardening cryptographic implementations with appropriate countermeasures is thus essential before they are deployed in the wild. However, countermeasures for both threats are of completely different nature: Side-channel analysis is mitigated by techniques that hide or mask key-dependent information while resistance against fault-injection attacks can be achieved by redundancy in the computation for immediate error detection. Since already the integration of any single countermeasure in cryptographic hardware comes with significant costs in terms of performance and area, a combination of multiple countermeasures is expensive and often associated with undesired side effects.

In this work, we introduce a countermeasure for cryptographic hardware implementations that combines the concept of a provably-secure masking scheme i.e., threshold implementation with an error detecting approach against fault injection. As a case study, we apply our generic construction to the lightweight LED cipher. Our LED instance achieves first-order resistance against side-channel attacks combined with a fault detection capability that is superior to that of simple duplication for most error distributions at an increased area demand of 12i¾?%.

ParTI --- Towards Combined Hardware Countermeasures Against Side-Channel and Fault-Injection Attacks

In the area of fault attacks, lasers are a common method to inject faults into an integrated circuit. Against the background of decreasing structure sizes in ICs, it is of interest which fault model can be met with state of the art equipment. We investigate laser-based fault injections into the SRAM-cells of block RAMs of two different FPGAs with 90i¾?nm and 45i¾?nm feature size respectively. Our results show that individual bit manipulations are feasible for both, the 90i¾?nm chip and the 45i¾?nm chip, but with limitations for the latter. To the best of our knowledge, we are the first to investigate laser fault injections into 45i¾?nm technology nodes. We provide detailed insights of our laser equipment and the parameters of our setupi¾?to give a comparison base for further research.

Precise Laser Fault Injections into 90-nm and 45-nm SRAM-cells

The use of a laser to inject faults into SRAM memory cells is well known. However, the corresponding fault model is often unknown or misunderstood: the induced faults may be described as bit-flip or bit-set/reset faults. We have investigated in this paper whether the bit-set/reset fault model or bit-flip fault model may be encountered in SRAMs. First, the fault model of a standalone SRAM was considered. Experiments revealed that the relevant fault model was the bit-set/reset. This result was further investigated through electrical simulations based on the use of an electrical model of MOS transistors under laser illumination. Then, fault injections have been performed on the RAM memory of a micro-controller to check the validity of the previous results based on experiments and simulations.

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Fault Model Analysis of Laser-Induced Faults in SRAM Memory Cells

This paper presents measurements of pulsed photoelectrical laser stimulation of an NMOS transistor in 90nm technology. The laser power was able to trig the NPN parasitic bipolar Drain/Psubstrate/Source. An electrical model is proposed in order to simulate effects induced by the laser. Results extracted from the electrical simulator are compared to measurements.

/pdf/building-the-electrical-model-of-the-pulsed-photoelectric-1r2jtt8rtx.pdf

Building the electrical model of the pulsed photoelectric laser stimulation of an NMOS transistor in 90nm technology

https://hal-emse.ccsd.cnrs.fr/emse-01094805/document

Improving the ability of Bulk Built-In Current Sensors to detect Single Event Effects by using triple-well CMOS

Bulk Built-In Current Sensors (BBICS) were developed to detect the transient bulk currents induced in the bulk of integrated circuits when hit by ionizing particles or pulsed laser This paper reports the experimental evaluation of a complete BBICS architecture, designed to simultaneously monitor PMOS and NMOS transistors, under Photoelectric Laser Stimulation (PLS) The obtained results are the first experimental proof of the efficiency of BBICS in laser fault injection detection attempts Furthermore, this paper highlights the importance of BBICS tapping in a sensitive area (logical gates) for improved laser detection It studies the performances of this BBICS architecture and suggests modifications for its future implementation

/pdf/experimental-validation-of-a-bulk-built-in-current-sensor-4hzfs9rv3t.pdf

Experimental validation of a Bulk Built-In Current Sensor for detecting laser-induced currents

Laser fault injection into SRAM cells is a widely used technique to perform fault attacks. In previous works, Roscian and Sarafianos studied the relations between the layout of the cell, its different laser-sensitive areas and their associated fault model using 50 ns duration laser pulses. In this paper, we report similar experiments carried out using shorter laser pulses (30 ps duration instead of 50 ns). Laser-sensitive areas that did not appear at 50 ns were observed. Additionally, these experiments confirmed the validity of the bit-set/bit-reset fault model over the bit-flip one. We also propose an upgrade of the simulation model they used to take into account laser pulses in the picosecond range. Finally, we performed additional laser fault injection experiments on the RAM memory of a microcontroller to validate the previous results.

/pdf/laser-fault-injection-into-sram-cells-picosecond-versus-49xft3b15k.pdf

Alexandre Sarafianos

Papers

Fault Model Analysis of Laser-Induced Faults in SRAM Memory Cells

Building the electrical model of the pulsed photoelectric laser stimulation of an NMOS transistor in 90nm technology

Improving the ability of Bulk Built-In Current Sensors to detect Single Event Effects by using triple-well CMOS

Experimental validation of a Bulk Built-In Current Sensor for detecting laser-induced currents

Laser fault injection into SRAM cells: Picosecond versus nanosecond pulses