The negative bias temperature instability in MOS devices: A review

Negative bias temperature instability (NBTI), in which interface traps and positive oxide charge are generated in metal–oxide–silicon (MOS) structures under negative gate bias, in particular at elevated temperature, has come to the forefront of critical reliability phenomena in advanced CMOS technology. The purpose of this review is to bring together much of the latest experimental information and recent developments in theoretical understanding of NBTI. The review includes comprehensive summaries of the basic phenomenology, including time- and frequency-dependent effects (relaxation), and process dependences; theory, including drift–diffusion models and microscopic models for interface states and fixed charge, and the role of nitrogen; and the practical implications for circuit performance and new gate-stack materials. Some open questions are highlighted. � 2005 Elsevier Ltd. All rights reserved.

Introductory Invited Paper The negative bias temperature instability in MOS devices: A review

An overview is presented of total ionizing dose (TID) effects in MOS and bipolar devices from a historical perspective, focusing primarily on work presented at the annual IEEE Nuclear and Space Radiation Effects Conference (NSREC). From the founding of the IEEE NSREC in 1964 until ~1976, foundational work led to the discovery of TID effects in MOS devices, the characterization of basic charge transport and trapping processes in SiO2, and the development of the first generations of metal-gate radiation-hardened MOS technologies. From ~1977 until ~1985, significant progress was made in the understanding of critical defects and impurities that limit the radiation response of MOS devices. These include O vacancies in SiO2, dangling Si bonds at the Si/SiO2 interface, and hydrogen. In addition, radiation-hardened Si-gate CMOS technologies were developed. From ~1986 until ~1997, a significant focus was placed on understanding postirradiation effects in MOS devices and implementing hardness assurance test methods to qualify devices for use in space systems. Enhanced low-dose-rate sensitivity (ELDRS) was discovered and investigated in linear bipolar devices and integrated circuits. From ~1998 until the present, an increasing focus has been placed on theoretical studies enabled by rapidly advancing computational capabilities, modeling and simulation, effects in ultra-thin oxides and alternative dielectrics to SiO2, and in developing a comprehensive model of ELDRS.

Total Ionizing Dose Effects in MOS and Low-Dose-Rate-Sensitive Linear-Bipolar Devices

Total ionizing dose radiation effects on the electrical properties of metal-oxide-semiconductor devices and integrated circuits are complex in nature and have changed much during decades of device evolution. These effects are caused by radiation-induced charge buildup in oxide and interfacial regions. This paper presents an overview of these radiation-induced effects, their dependencies, and the many different approaches to their mitigation.

Radiation effects and hardening of MOS technology: devices and circuits

Low-Frequency Noise in Advanced CMOS Devices begins with an introduction to noise, describing the fundamental noise sources and basic circuit analysis. The characterization of low-frequency noise is discussed in detail and useful practical advice is given. The various theoretical and compact low-frequency (1/f) noise models in MOS transistors are treated extensively providing an in-depth understanding of the low-frequency noise mechanisms and the potential sources of the noise in MOS transistors. Advanced CMOS technology including nanometer scaled devices, strained Si, SiGe, SOI, high-k gate dielectrics, multiple gates and metal gates are discussed from a low-frequency noise point of view. Some of the most recent publications and conference presentations are included in order to give the very latest view on the topics. The book ends with an introduction to noise in analog/RF circuits and describes how the low-frequency noise can affect these circuits.

Low-Frequency Noise in Advanced MOS Devices

A method for separation and calculation of gate oxide and surface state charges in CMOS transistors have been developed, leading to a significant improvement of the analysis of CMOS integrated circuit instabilities. In order to demonstrate the usefulness of the method, an analysis of instabilities in transistors subject to high electric field and high temperature-bias stress has been carried out. Four instability mechanisms associated with high electric field stress are observed. Successively we consider a positive gate oxide charge increase due to hole tunneling from the silicon valence band into oxide hole traps (in case of negative gate bias), electron tunneling from oxide electron traps into the oxide conduction band (in case of positive gate bias), and a surface state charge increase due to tunneling of electrons from the metal to the silicon (in case of negative gate bias) or from the silicon to the metal (in case of positive gate bias). In addition instabilities associated with high temperature-bias stress are observed: drift of mobile ions in the gate oxide, increase of positive trapped charge in the gate oxide and simultaneous increase of the surface state and negative gate oxide charges.

Analysis of CMOS transistor instabilities

Logic and Computer Design Fundamentals

The applicability of charge-pumping technique to characterize the oxide/silicon interface in standard power Vertical Double-diffused (VD)MOS transistors is studied. Qualitative analysis of the charge-pumping threshold and flat-band voltage distributions in the VDMOS structure, supported with rigorous transient numerical modeling of the charge-pumping effect, shows that the measurements can be carried out in the subthreshold region. This conclusion is confirmed by various experimental results. The characteristics, i.e. charge-pumping current versus gate top level, is studied in detail. The changes in the characteristics after /spl gamma/-ray irradiation are analyzed. A charge-pumping-based method for separate extraction of interface state density and density of charge trapped in the oxide after irradiation of VDMOSFETs is proposed. The validity and limitations of the method are studied by experiments and modeling.

Ninoslav Stojadinovic

Papers

Analysis of CMOS transistor instabilities

Logic and Computer Design Fundamentals

Charge-pumping characterization of SiO/sub 2//Si interface in virgin and irradiated power VDMOSFETs

Negative bias temperature instability mechanisms in p-channel power VDMOSFETs

The determination of zero temperature coefficient point in CMOS transistors