P
Patrick Gallagher
Researcher at Cadence Design Systems
Publications - 24
Citations - 422
Patrick Gallagher is an academic researcher from Cadence Design Systems. The author has contributed to research in topics: Automatic test pattern generation & Cache pollution. The author has an hindex of 11, co-authored 24 publications receiving 419 citations. Previous affiliations of Patrick Gallagher include IBM.
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Patent
Shared two level cache including apparatus for maintaining storage consistency
TL;DR: In this paper, a multilevel cache buffer for a multiprocessor system is described, where each processor has a level one cache storage unit which interfaces with a level two cache unit and main storage unit shared by all processors.
Patent
Method and mechanism for implementing electronic designs having power information specifications background
Qi Wang,Ankur Gupta,Pinhong Chen,Christina Chu,Manish Pandey,Huan-Chih Tsai,Sandeep Bhatia,Yonghao Chen,Steven Sharp,Vivek Chickermane,Patrick Gallagher +10 more
TL;DR: In this article, a method of adding power control circuitry to a circuit design at each RTL and a netlist level comprising demarcating multiple power domains within the circuit design, specifying multiple power modes each power mode corresponding to a different combination of on/off states of the multiple demarcated power domains, and defining isolation behavior relative to respective power domains is presented.
Patent
Hierarchical computer cache system
James Wilson Bishop,Charles Embrey Carmack,Patrick Gallagher,Stefan Peter Jackowski,Gregory R. Klouda,Robert Dwight Siegl +5 more
TL;DR: In this paper, a page mover is coupled to the higher level cache subsystem and main memory, and responds to a request from one of the CPUs to store data into the main memory.
Proceedings ArticleDOI
Capture power reduction using clock gating aware test generation
TL;DR: By taking advantage of the existing clock gating circuitry and selectively holding the value of some scan flip-flops, switching activity during the capture cycles of a test can be reduced.
Proceedings ArticleDOI
A Power-Aware Test Methodology for Multi-Supply Multi-Voltage Designs
TL;DR: A novel solution to address the manufacturing test of an MSMV/PSO design is described by using power-mode specifications to map multiple power modes to their target test modes and enhancing the DFT and ATPG methodology to enable a comprehensive test methodology.