Journal ArticleDOI
Design and characteristics of the lightly doped drain-source (LDD) insulated gate field-effect transistor
TLDR
In this paper, a self-aligned n-regions are introduced between the channel and the n+source-drain diffusions of an IGFET to spread the high field at the drain pinchoff region and thus reduce the maximum field intensity.Abstract:
The LDD structure, where narrow, self-aligned n-regions are introduced between the channel and the n+source-drain diffusions of an IGFET to spread the high field at the drain pinchoff region and thus reduce the maximum field intensity, is analyzed. The design is shown, including optimization of the n-dimensions and concentrations and the boron channel doping profile and an evaluation of the effect of the series resistance of the n-regions on device transconductance. Characteristics of experimental devices are presented and compared to those of conventional IGFET's. It is shown that significant improvements in breakdown voltages, hot-electron effects, and short-channel threshold effects can be achieved allowing operation at higher voltage, e.g., 8.5 versus 5 V, with shorter source-drain spacings, e.g., 1.2 versus 1.5 µm. Alternatively, a shorter channel length could be used for a given supply voltage. Performance projections are shown which predict 1.7 × basic device/circuit speed enhancement over conventional structures. Due to the higher voltages and higher frequency operation, the higher performance results in an increase in power which must be considered in a practical design.read more
Citations
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Journal ArticleDOI
CMOS scaling for high performance and low power-the next ten years
TL;DR: In this article, a guideline for scaling of CMOS technology for logic applications such as microprocessors is presented covering the next ten years, assuming that the lithography and base process development driven by DRAM continues on the same three-year cycle as in the past.
Patent
Method for Manufacturing Semiconductor Device
TL;DR: In this article, the authors proposed a method for manufacturing a semiconductor device, in which the number of photolithography steps can be reduced, the manufacturing process can be simplified, and manufacturing can be performed with high yield at low cost.
Journal ArticleDOI
Hot-electron-induced photon and photocarrier generation in Silicon MOSFET's
Simon M. Tam,Chenming Hu +1 more
TL;DR: In this article, the phenomenon of and the physical mechanisms for the generation of minority carriers in the substrate of NMOS and CMOS are studied and a theoretical model based on the lucky electron concept and the bremsstrahlung mechanism is proposed.
Journal ArticleDOI
Anomalous leakage current in LPCVD PolySilicon MOSFET's
TL;DR: The anomalous leakage current I L in LPCVD polysilicon MOSFETs is attributed to field emission via grain-boundary traps in the (front) surface depletion region at the drain, and an analytic model that describes the strong dependences of I L on the gate and drain voltages is developed.
Journal ArticleDOI
Gate-voltage-dependent effective channel length and series resistance of LDD MOSFET's
G.J. Hu,Chi Chang,Yu-Tai Chia +2 more
TL;DR: In this article, a measurement algorithm to extract the effective channel length and source-drain series resistance of MOSFET's is presented, which is applicable to both conventional and LDD FET's.
References
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Journal ArticleDOI
Design of ion-implanted MOSFET's with very small physical dimensions
TL;DR: This paper considers the design, fabrication, and characterization of very small Mosfet switching devices suitable for digital integrated circuits, using dimensions of the order of 1 /spl mu/.
Journal ArticleDOI
Emission probability of hot electrons from silicon into silicon dioxide
T. H. Ning,C.M. Osburn,H. N. Yu +2 more
TL;DR: In this paper, an experimental method is described for directly measuring the probability of electron emission from the silicon substrate into the SiO2 layer after the electron has fallen through a certain potential drop in traversing the depletion layer and reached the SiSiO2 interface.
Journal ArticleDOI
1 µm MOSFET VLSI technology: Part IV—Hot-electron design constraints
TL;DR: In this paper, an approach for determining the hot-electron-limited voltages for silicon MOSFET's of small dimensions was described. But the approach was not followed in determining the room-temperature and the 77 K hotelectron limited voltages of a device designed to have a minimum channel length.
Journal ArticleDOI
VLSI limitations from drain-induced barrier lowering
TL;DR: In this paper, the important design parameters relating to Drain-Induced Barrier lowering (DIBL) are investigated using a numerical two-dimensional model, and a simple conceptual model is introduced as an aid for understanding the results.
Journal ArticleDOI
A numerical model of avalanche breakdown in MOSFET's
TL;DR: In this article, an accurate numerical model of avalanche breakdown in MOSFETs is presented, which uses an accurate electric field distribution calculated by a two-dimensional numerical analysis, and introduces multiplication factors for a high-field path and the channel current path.