Showing papers by "Paul S. Ho published in 2006"

Electromigration enhanced intermetallic growth and void formation in Pb-free solder joints

Abstract: A kinetic analysis was formulated for electromigration enhanced intermetallic evolution of a Cu–Sn diffusion couple in the Sn-based Pb-free solder joints with Cu under bump metallurgy. The simulated diffusion couple comprised the two terminal phases, Cu and Sn, as well as the two intermetallic phases, Cu3Sn and Cu6Sn5, formed between them. The diffusion and electromigration parameters were obtained by solving the inverse problem of the electromigration enhanced intermetallic growth, and they were compatible with the literature values. Finite difference method was applied to the whole simulated domain to solve for the mass transport kinetics within the intermetallic phases and across each interface of interest. Simulation showed that, when electromigration effect was absent (zero current), intermetallic growth followed a parabolic law, suggesting a diffusion controlled mechanism for thermal aging. However, under significant current stressing (4×104A∕cm2), the growth of the dominant intermetallic Cu6Sn5 cle...

Effect of contact metallization on electromigration reliability of Pb-free solder joints

Abstract: The effect of underbump metallization (UBM) on electromigration (EM) lifetime and failure mechanism has been investigated for Pb-free solder bumps of 97Sn3Ag composition in the temperature range of 110–155°C. The EM lifetime of the SnAg Pb-free solders with either Cu or Ni UBM was found to be better than the eutectic SnPb (63Sn37Pb) solders but worse than high-Pb (95Pb5Sn) solders. In the test temperature range, the EM lifetimes were found to be comparable for Cu and Ni UBMs but with different activation energies: 0.64–0.72eV for Cu UBM and 1.03–1.11eV for Ni UBM. EM failure was observed only in solder bumps with electron current flow from UBM to the substrate. Failure analysis revealed that EM damage was initiated by the formation of intermetallic compounds (IMC) at the UBM∕solder interface which was found to be significantly enhanced by mass transport driven by the electron current. Under EM, the continued growth of IMC with the dissolution of the UBM and the accumulation of Kirkendall voids resulted in...

Electromigration statistics and damage evolution for Pb-free solder joints with Cu and Ni UBM in plastic flip-chip packages

Abstract: A series of electromigration (EM) tests were performed as a function of temperature and current density to investigate lifetime statistics and damage evolution for Pb-free solder joints with Cu and Ni under-bump-metallizations (UBMs). The EM lifetime was found to depend on the failure criterion used, so the results were compared based on the first resistance jump and conventional open-failure criterion. Solder joints with Cu UBM had a longer lifetime than Ni UBM based on the open-failure criterion, but the lifetime with Ni UBM became comparable when the first resistance jump criterion was applied. To determine the temperature in solder joints, the Joule heating effect was investigated with experiments and finite element analysis. The temperature of solder joints was determined to be approximately 15°C higher than that at the Si die surface when 1 A of current was applied. With the appropriate temperature correction, the activation energies and the current density exponents were found to be Q = 1.11 eV, n = 3.75 and Q = 0.86 eV, n = 2.1 based on the open-failure criterion for solder joints with Cu and Ni UBM, respectively. Based on the first resistance jump criterion, Q = 1.05 eV, n = 1.45 for Cu UBM and Q = 0.94 eV, n = 2.2 for Ni UBM, respectively. For solder joints with Cu UBM, voids were formed initially at the Cu6Sn5/solder interface while the final open failure occurred at the Cu3Sn/Cu6Sn5 interface. For Ni UBM, voids were formed initially at the Ni3Sn4/solder interface leading to failure at the same interface. The formation of intermetallic compounds (IMCs) was enhanced under current stressing, which followed linear growth kinetics with time. The IMC growth was accompanied by volume shrinkage, which accelerated damage evolution under EM.

Effect of passivation on stress relaxation in electroplated copper films

Abstract: The present study investigated the effect of passivation on the kinetics of interfacial mass transport by measuring stress relaxation in electroplated Cu films with four different cap layers: SiN, SiC, SiCN, and a Co metal cap. Stress curves measured under thermal cycling showed different behaviors for the unpassivated and passivated Cu films, but were essentially indifferent for the films passivated with different cap layers. On the other hand, stress relaxation measured under an isothermal condition revealed clearly the effect of passivation, indicating that interface diffusion controls the kinetics of stress relaxation. The relaxation rates in the passivated Cu films were found to decrease in the order of SiC, SiCN, SiN, and metal caps. This correlates well with previous studies on the relationship between interfacial adhesion and electromigration. A kinetic model based on coupling of interface and grain-boundary diffusion was used to deduce the interface diffusivities and the corresponding activation energies.

Effect of supporting layer on growth of carbon nanotubes by thermal chemical vapor deposition

Abstract: Selective growth of vertically aligned and highly dense carbon nanotubes was achieved by using thermal chemical vapor deposition via careful selection of a thin catalyst layer and an appropriate supporting layer. It was found that carbon nanotube growth was significantly enhanced when tantalum was used as the supporting layer on which a thin iron catalyst was deposited. Cross-sectional transmission electron microscopy revealed a Stranski-Krastanov mode of iron island growth on tantalum with relatively small contact angles controlled by the relative surface energies of the supporting layer, the catalyst, and their interface. The as-formed iron island morphology promoted vertical growth of carbon nanotubes.

Chip‐Packaging Interaction and Reliability Impact on Cu/Low k Interconnects

Abstract: The packaging process can increase the driving force for interfacial delamination and significantly impacts the reliability of the low k chip. In this study we investigated the packaging effect due to die attach process where a high thermal load occurs during solder reflow before underfilling. With the high thermal load and without the underfill, the chip‐package interaction is maximized and can become most detrimental to low k chip reliability. Both SiLK and MSQ dielectrics were investigated to examine the influence of low k properties on packaging reliability. In addition to different low k dielectrics, we investigated the effects due to the substrate material, die size and solder materials, including the lead‐free solder. The packaging effect was found to be higher for flip‐chip packages with lead‐free solder than the eutectic lead solder and the high lead solders. Flip‐chip packages with a ceramic substrate were found to have a smaller packaging effect than that with a plastic substrate. Increasing die size increases the crack driving force for low k interfacial delamination, as expected. Packaging effect was generally lower for the Cu/MSQ structure than for the Cu/SiLK structure, and the difference can be attributed to the higher Young’s modulus of the MSQ material.

Electromigration lifetime statistics for Pb-free solder joints with Cu and Ni UBM in plastic flip-chip packages

Abstract: A series of electromigration tests were performed as a function of temperature and current density to investigate lifetime statistics for Pb-free solder with Cu or Ni under-bump-metallization (UBM). Based on the overall shape of resistance traces, a conservative failure criterion for time-to-failure was defined and the results were compared with those based on the conventional open-failure criterion. Solder joints with Cu UBM had a longer lifetime than with Ni UBM, based on the open-failure criterion; however, the lifetime with Ni UBM became comparable when the conservative criterion was applied. The Joule heating effect was accounted for based on experiments and finite element analysis. The temperature of solder joints was determined to be approximately 15/spl deg/C higher than that at the Si die surface when 1 A of current was passed. For solder with Cu UBM, voids formed initially at the Cu/sub 6/Sn/sub 5//solder interface while the final open failure occurred at the Cu/sub 3/Sn/Cu/sub 6/Sn/sub 5/ interface. For Ni UBM, voids formed initially at the Ni/sub 3/Sn/sub 4//solder interface leading to failure at the Ni/sub 3/Sn/sub 4//solder interface.

Analysis of electromigration statistics for Cu interconnects

Abstract: Electromigration failure statistics and the origin of the lognormal standard deviation for copper interconnects were investigated by analyzing the statistics of electromigration lifetimes and void size distributions at various stages during testing. A statistical correlation between electromigration lifetimes and void evolution was established. Using simulation to fit the experimental data, the parameters influencing the electromigration lifetime statistics were identified as variations in void sizes, geometrical and experimental factors of the electromigration experiment, and kinetic aspects of the mass transport process, such as differences in the interface diffusivity between the lines.

Investigation of residual stress in wafer level interconnect structures induced by wafer processing

Abstract: Wafer processing induced residual stress in wafer level Cu interconnect structures can have a significant impact on reliability of Cu interconnects. In this study, a finite element analysis approach based on element birth and death technique was developed to simulate the wafer processing procedure. Residual stress in the wafer structures at each processing step was obtained. Wafer processing procedures for Cu single damascene structures were first simulated and the results were verified with stresses measured by X-ray techniques. After the FEA model was verified, Cu dual damascene structures were studied in detail. Residual stress obtained from FEA was used to explain the stress-induced voiding phenomenon at the bottom of via after wafer processing.

Effects of Chip-Package Interaction on Mechanical Reliability of Cu Interconnects for 65nm Technology Node and Beyond

Abstract: The impact of chip-package interaction (CPI) on the mechanical reliability of Cu low-k interconnects was investigated using a 3D multi-level sub-modeling method. The analysis was focused on the die attach process for Pb-free solder where a high thermal load will occur during solder reflow before underfilling to maximize the packaging effect. We compared first the CPI for a CVD-OSG (k=3.0) with MSQ (k=2.7) and spin-on polymer (k=2.7) to investigate how better material properties can improve interconnect reliability. Then the study was extended to porous MSQ (k=2.3) to examine CPI for the 65nm node and beyond. Finally, requirements of the mechanical properties of low-k ILD for improving interconnect reliability are discussed

Effect of barrier process on electromigration reliability of Cu/porous low-k interconnects

Abstract: Electromigration (EM) reliability of Cu/low-k interconnects with a conventional preclean-first process, and an advanced barrier-first process has been investigated. Compared with the preclean-first process, extrinsic early failures were not observed for the barrier-first process. This suggests that process-induced defects, which are the most probable cause for early failures, are significantly reduced for the barrier-first process. Transmission electron microscopy observation demonstrated a more uniform and thicker Ta barrier for the barrier-first process than the preclean-first process. This led to a higher (jL)c product, and prolonged the EM lifetime accordingly. In addition, a predeposited Ta barrier during the barrier-first process protected the mechanically weak low-k dielectrics from plasma etch damage, and a uniform via profile resulted. In contrast, the via opening at the top was found to be larger than that of at the via bottom for the preclean process. The uniform via profile is another advantag...

Planarization for reverse-tone step and flash imprint lithography

Abstract: Understanding the dynamics of thin film planarization over topography is a key issue in the reverse-tone step and flash imprint lithography (SFIL-R) process. Complete planarization of a film over large, isolated topography poses an enormous challenge, since the driving force for planarization, the capillary pressure, continuously weakens as the film becomes more planar. For SFIL-R, only a specific degree of planarization (DOP) needs to be achieved before pattern transfer is possible. This paper presents the derivation of an inequality statement describing the required extent of planarization for successful pattern transfer. To observe how this critical DOP value (DOPcrit), and its corresponding leveling time (Tcrit) vary with materials and topographic properties, finite difference simulation was utilized to model planarization of a thin film over isolated topography after the spincoating process. This model was verified experimentally for various film thickness to substrate height ratios using interferometry to monitor silicon oil planarization over isolated trenches and lines. Material and topographic parameters were shown to not have a dramatic impact on DOPcrit; however, the critical leveling time increased considerably at DOPcrit values above 60 percent.

Materials effects on reliability of FC-PBGA packages for Cu/low-k chips

Abstract: Reliability of the flip-chip plastic ball grid array (FC-PBGA) packages is highly dependent on the properties of the constituent components and the interface formed between them. The relative mechanical compliances and thermal mismatch between the silicon chip, the underfill material and the organic laminate substrate are particularly important to the design and performance the package. Strong coupling between the chip and the substrate can cause chip cracking, delamination of interlayer dielectrics (ILD), delamination of underfill and problems associated with BGA interconnection when the package is assembled to a printed circuit board (PCB). The problem became more severe as we migrate to the 90nm and 65nm silicon technology nodes where low-k ILD is widely used. Combined experimental and modeling methods were used to investigate the thermo-mechanical behavior and failure mechanisms controlling FC-PBGA package reliability. Materials effect of new generation of underfill materials was first studied for minimizing the chip-substrate thermo-mechanical coupling. Fully assembled FC-PBGA packages with various underfill materials were evaluated following a carefully designed analysis and screening flow. Thermo-mechanical response of the package was measured and analyzed using high resolution moire interferometry and numerical modeling techniques. Four-point bending test was also used to characterize interfacial fracture energy for the critical interface between die passivation and underfill material. The experiments and modeling were correlated with the JEDEC standard component-level reliability testing results. The combined experimental and numerical analysis confirmed our selection of the substrate, underfill and other package materials and demonstrated that significantly improved reliability of the flip-chip PBGA packages can be achieved by controlling thermo-mechanical coupling of the silicon die and the package, and by controlling various important interfaces within the package.

Statistical Analysis of Electromigration Lifetimes for Cu Interconnects

Abstract: Electromigration (EM) failure statistics and the origin of the lognormal standard deviation (σ) for Cu interconnects have been investigated by analyzing the statistics of lifetime and void size distributions at various stages during EM testing. Experiments were performed on 0.18μm wide, single damascene Cu interconnects with tests terminated after certain amounts of resistance increase, or after a specified test time. Void size distributions of resistance‐based and time‐based EM tests were obtained. The σ values of lifetime and void size distributions showed a significant decrease with increasing resistance failure criterion. The statistics of resistance‐based void size distributions can be explained by considering geometrical variations of the void shape, while the characteristics of time‐based void size distributions require consideration of kinetic aspects of the EM process. The σ values of EM lifetime distributions can be adequately simulated by combining the statistics of both types of void size distributions. Thus, using simulation to fit the experimental data, the parameters influencing the EM lifetime statistics were identified as variations in void sizes, geometrical and experimental factors of the EM test and kinetic aspects of the mass transport process, such as differences in interface diffusivity between the lines. The variation in diffusivities at the cathode ends of the lines are a result of varying Cu grain orientations. Furthermore, the analysis of the EM statistics of samples with a reduced line height and dual damascene processing will be presented.

Advanced Preclean for Integration of PECVD SiOCH (k=2.5) Dielectrics with Copper Metallization Beyond 45nm Technology

Abstract: Preclean is a critical process step in Cu metallization to ensure device reliability. For the integration of ultra low k (kles2.5) dielectrics, an advanced preclean (APC) technology has been developed and characterized using PECVD SiOCH (k=2.5) dielectrics. With the optimal hardware and process, this technology minimizes plasma damage, causing no measurable k increase and having the lowest impact to other properties of the low k film. At the same time it effectively removes etch residues in dielectric structures and native oxides on the underneath metal surface prior to Cu barrier deposition. The electrical tests demonstrated that APC not only met the reliability requirements for typical BEOL structures but also significantly reduced line-to-line capacitance degradation over ultra low k structures, offering a superior alternative to the conventional preclean technologies

Oxidation of the TA Diffusion Barrier and Its Effect on the Reliability of CU Interconnects

Abstract: The oxidation of the Ta diffusion barrier and its effect on the reliability of Cu interconnects were investigated by high temperature storage (HTS) and via-to-line biased temperature stressing (BTS) tests. Cu/FSG, Cu/OSG, and Cu/porous low-k interconnects were investigated in vacuum (~ 1 torr), 0.1 atm air, and air. The exponential increase of resistance over the entire temperature range of the test was commonly found during HTS in via-chain test structures of all interconnects. It was different from typical stress migration behavior as the failure rate did not exhibit a peak at an intermediate temperature but increased exponentially with temperature. No voids were found in the failed samples that had resistance increases up to infinity. Instead, the Ta diffusion barrier was oxidized partially according to transmission electron microscopy/electron energy-loss spectroscopy (TEM/EELS) analysis. The oxidation of the Ta barrier at the via bottom was determined to be the cause of the electrical failure during HTS, which agreed with experimental results. During HTS tests, the Ta diffusion barrier was found to be more oxidized at the via sidewalls than at the M1 or M2 trench sidewalls. This oxidized Ta barrier at the via sidewalls was less protective. In the case of Cu/porous low k interconnects, Cu was found to diffuse out through the oxidized barrier at the via sidewalls, whereas Cu out-diffusion through the M1 or M2 trench sidewall was not noticeable. In via-to-line BTS tests, failure was also found to be caused by Cu out-diffusion/drift through the oxidized Ta diffusion barrier at the via sidewalls. The preferential oxidation of the Ta barrier at the via sidewalls and Cu out-diffusion through it suggests that the Ta barrier was more oxidizable and more permeable at the via sidewalls than at the M1 or M2 trench sidewall. Among the three kinds of interconnects used in this study, Cu/porous low-k was the most susceptible to the Ta diffusion barrier oxidation

Impact of chip-package interaction on reliability of Cu/ultra low-k interconnects for 65nm technology and beyond

Abstract: The die attach process to flip chip package using Pb-free solder can impact the mechanical reliability of Cu/ultra low-k interconnects for 65nm technology and beyond. In this study, chip-package interaction (CPI) during solder reflow before underfilling was investigated by using a 3D multilevel submodeling method and by calculating the crack driving force at the specific interface in the Cu/Ultra low-k interconnects. We compared first the CPI for a CVD-OSG (k = 3.0) with MSQ (k = 2.7) and spin-on polymer (k = 2.7) to investigate how the material properties affects the interconnect reliability. Then the study was extended to porous MSQ (k = 2.3) to examine CPI for the 65 nm node and beyond. Packaging effects were significantly changed with different Young's modulus but was not changed with different coefficient of thermal expansion (CTE). Further results are shown with different interconnect structures. Finally, requirements of the mechanical properties of low-k interlayer dielectric (ILD) and the interconnect structure for improving interconnect reliability are discussed

Kinetic Analysis of Current Enhanced Intermetallic Growth and Its Effect on Electromigration Reliability of Solder Joints

Abstract: A kinetic analysis was formulated for electromigration induced intermetallics evolution of a Cu-Sn diffusion couple. Simulation of the time dependency of intermetallic growth is consistent with experimental data showing growth and accumulation of a high concentration of vacancies and formation of Kirkendall voids at the Cu6Sn5 side of the Cu3Sn/Cu6Sn5 interface.

Electromigration Reliability of 60 nm Dual Damascene Cu Interconnects

Abstract: Electromigration (EM) reliability was investigated for 60 nm wide lines fabricated using a SiON (siliconoxynitride) trench-filling process. EM was observed to be dominated by intrinsic failures due to void formation in the line trench. The lifetime was longer than that of a standard damascene structure, which can be attributed to a distinct via/metal-1 configuration in reducing process-induced defects at the via interface. The line scaling effect on EM reliability was investigated using three different line widths: 60 nm, 110 nm, and 185 nm. EM lifetimes were found to be similar for the different line widths, which is consistent with intrinsic failures due to void formation in the line trench. With a dense and stable SiON filling layer, the processing and thickness effects of the Ta barrier on EM reliability were found to be less significant than for Cu/low-k structures. Multi-linked EM test structures revealed no early failure in the 60 nm samples with a SiON filling layer, although process control of line dimension and geometry remained an issue

Critical and Sub-critical Debonding in Nano-clustering Porous Low-k Films

Abstract: Very few porous low-k dielectric materials meet the basic requirements for integration into the back end of the line (BEOL) metallization. According to the International Technology Roadmap for Semiconductors, 2005, candidates for the 45 nm node need a k<2.2 and a minimum adhesion strength of 5 J/m2. Recently, a low-k dielectric material was developed, called nano-clustered silica (NCS). It is a spin-on glass with k<2.3. NCS is constitutively porous, with a micro- and mesopore size of ~2.8 nm. The first reported adhesion strength of this material was 10+ J/m2. We investigated the nature of the adhesive strength of NCS by critical and sub-critical fracture and Fourier Transform IR Spectroscopy (FTIR). The four-point bend technique and a mixed-mode double cantilever beam technique were employed. The sub-critical crack growth studies were performed in humid environments and ambient temperatures. Different post-treatments were used on NCS to achieve different molecular structure, as measured with FTIR. A correlation between molecular structure and critical adhesion energy was found. Atomistic parameters were calculated from the sub-critical crack growth data. A dependency of fracture behavior on post-treatment and, therefore, structure was observed.

Fracture Behavior and Mechanical Properties of Porous Low‐k Materials

Abstract: The weak mechanical properties of porous low‐k dielectric materials raise a major reliability concern for implementation into on‐chip interconnects. Mechanical properties of the conventional template‐type materials deteriorate with increasing porosity due to the formation of open pores and pore channels during template evaporation. For this reason, NCS (Nano‐Clustering Silica) which is a non‐template type of porous material was developed as a low‐k dielectric for the 65nm technology node and beyond. The NCS material has an elastic modulus higher than 10 GPa because only closed pores are formed and the pore size do not change during the curing process. This paper investigated the fracture behavior of the NCS material using four point bending and DCB (Double Cantilever Beam) tests to measure interfacial fracture energy and sub‐critical crack growth rate. Crack formation was found to occur via cohesive fracture with cracks mainly confined within the matrix. The effect of curing on the molecular structure of ...