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Paul W. Coteus
Researcher at IBM
Publications - 233
Citations - 8373
Paul W. Coteus is an academic researcher from IBM. The author has contributed to research in topics: Interposer & Land grid array. The author has an hindex of 43, co-authored 233 publications receiving 8236 citations. Previous affiliations of Paul W. Coteus include GlobalFoundries.
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Patent
Method and system for providing frame start indication in a memory system having indeterminate read data latency
TL;DR: In this paper, a method and system for providing frame start indication in a memory system having indeterminate read data latency is presented, which includes receiving a data transfer and determining if the data transfer includes a frame start indicator.
Patent
T-star interconnection network topology
Dong Chen,Paul W. Coteus,Noel A. Eisley,Philip Heidelberger,Robert M. Senger,Yutaka Sugawara +5 more
TL;DR: In this article, a method of constructing network communication for a grid of node groups is provided, the grid including an M dimensional grid, each node group including N nodes, wherein M is greater than or equal to one and N is more than one, wherein each node includes a router.
Patent
Method and system for providing identification tags in a memory system having indeterminate data response times
TL;DR: In this paper, a memory controller includes a mechanism for receiving data packets via an upstream channel, the data packets including upstream identification tags, and a mechanism having instructions for facilitating determining if a received data packet is in response to a request from the memory controller.
Patent
Planar array contact memory cards
TL;DR: A Planar Memory Module (PAMM) as mentioned in this paper is a planar memory device comprising a generally planar card comprising a first side and a second side, the first side having a plurality of couplings and the second side having an associated one of the connectors.
Patent
System and method for providing a memory device having a shared error feedback pin
TL;DR: In this article, the authors present a system and method for providing a memory device having a shared error feedback feedback pin, which includes CRC receiving circuitry for the detection of errors in one or more of the received data and the received CRC bits.