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Paul W. Coteus

Researcher at IBM

Publications -  233
Citations -  8373

Paul W. Coteus is an academic researcher from IBM. The author has contributed to research in topics: Interposer & Land grid array. The author has an hindex of 43, co-authored 233 publications receiving 8236 citations. Previous affiliations of Paul W. Coteus include GlobalFoundries.

Papers
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Proceedings Article

Frequency-dependent crosstalk simulation for on-chip interconnections

TL;DR: In this article, an extensive study of crosstalk simulation issues for on-chip interconnections was performed for representative six-layer Al(Cu) structures, and the results were verified through measurement of a comprehensive set of experiments built with a large range of line widths and spaces on various layers with both in-plane and vertical coupling.
Patent

Learning-based thermal estimation in multicore architecture

TL;DR: In this paper, a trained neural network with the hardware resource utilization data associated with the application is run, and the network predicts core temperature associated with running the application on a core of the hardware processor.
Patent

Land grid array (LGA) interposer structure providing for electrical contacts on opposite sides of a carrier plane

TL;DR: A land grid array (LGA) interposer as discussed by the authors is composed of a hemi-toroidal configuration in transverse cross-section and is constituted of a dielectric elastomeric material.