Paul W. Coteus

TL;DR: In this paper, a design structure for a 3D chip having at least one I/O layer connected to other three-dimensional (3D) chip layers by a vertical bus is presented, such that the IO layer(s) may accommodate protection and off-chip device drive circuits, customization circuits, translation circuits, conversions circuits and/or built-in self-test circuits capable of comprehensive chip or wafer level testing wherein the I/Os layers function as a testhead.

TL;DR: In this article, a ground detection circuit was proposed for detecting the presence/absence of adapter cards such as memory modules and alike, which can be combined with different signals emanating from the memory modules such that when one or more of the adapter cards are absent, a default value resulting from the absence of ground is used to indicate the missing adapter(s).

TL;DR: In this paper, an experimental high-speed characterization and electrical modeling and simulation for a six-layer Cu/SiO/sub 2/ on-chip wiring structure with 12.4mm-long lines is presented.

TL;DR: In this paper, a multiprocessor, parallel computer is made tolerant to hardware failures by providing extra groups of redundant standby processors and by designing the system so that these extra groups can be swapped with any group which experiences a hardware failure.

TL;DR: In this paper, a method for monitoring full performance of a file system (100) in the presence of a failure is provided, including switching the connection of one of the N storage devices to the secondary file server upon a failure of one N primary file servers; and switching the connections of one or more of the remaining storage device to a primary file server other then the failed file server as necessary so as to prevent a loss in performance and provide each storage device with an operating file server.