Three parallel algorithms for classical molecular dynamics are presented. The first assigns each processor a fixed subset of atoms; the second assigns each a fixed subset of inter-atomic forces to compute; the third assigns each a fixed spatial region. The algorithms are suitable for molecular dynamics models which can be difficult to parallelize efficiently—those with short-range forces where the neighbors of each atom change rapidly. They can be implemented on any distributed-memory parallel machine which allows for message-passing of data between independently executing processors. The algorithms are tested on a standard Lennard-Jones benchmark problem for system sizes ranging from 500 to 100,000,000 atoms on several parallel supercomputers--the nCUBE 2, Intel iPSC/860 and Paragon, and Cray T3D. Comparing the results to the fastest reported vectorized Cray Y-MP and C90 algorithm shows that the current generation of parallel machines is competitive with conventional vector supercomputers even for small problems. For large problems, the spatial algorithm achieves parallel efficiencies of 90% and a 1840-node Intel Paragon performs up to 165 faster than a single Cray C9O processor. Trade-offs between the three algorithms and guidelines for adapting them to more complex molecular dynamics simulations are also discussed.

Fast parallel algorithms for short-range molecular dynamics

Today's data centers may contain tens of thousands of computers with significant aggregate bandwidth requirements. The network architecture typically consists of a tree of routing and switching elements with progressively more specialized and expensive equipment moving up the network hierarchy. Unfortunately, even when deploying the highest-end IP switches/routers, resulting topologies may only support 50% of the aggregate bandwidth available at the edge of the network, while still incurring tremendous cost. Non-uniform bandwidth among data center nodes complicates application design and limits overall system performance.In this paper, we show how to leverage largely commodity Ethernet switches to support the full aggregate bandwidth of clusters consisting of tens of thousands of elements. Similar to how clusters of commodity computers have largely replaced more specialized SMPs and MPPs, we argue that appropriately architected and interconnected commodity switches may deliver more performance at less cost than available from today's higher-end solutions. Our approach requires no modifications to the end host network interface, operating system, or applications; critically, it is fully backward compatible with Ethernet, IP, and TCP.

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A scalable, commodity data center network architecture

Power dissipation is a fundamental problem for nanoelectronic circuits. Scaling the supply voltage reduces the energy needed for switching, but the field-effect transistors (FETs) in today's integrated circuits require at least 60 mV of gate voltage to increase the current by one order of magnitude at room temperature. Tunnel FETs avoid this limit by using quantum-mechanical band-to-band tunnelling, rather than thermal injection, to inject charge carriers into the device channel. Tunnel FETs based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction over complementary metal-oxide-semiconductor (CMOS) transistors, so integrating tunnel FETs with CMOS technology could improve low-power integrated circuits.

Tunnel field-effect transistors as energy-efficient electronic switches

Concern about the performance of wires wires in scaled technologies has led to research exploring other communication methods. This paper examines wire and gate delays as technologies migrate from 0.18-/spl mu/m to 0.035-/spl mu/m feature sizes to better understand the magnitude of the the wiring problem. Wires that shorten in length as technologies scale have delays that either track gate delays or grow slowly relative to gate delays. This result is good news since these "local" wires dominate chip wiring. Despite this scaling of local wire performance, computer-aided design (CAD) tools must still become move sophisticated in dealing with these wires. Under scaling, the total number of wires grows exponentially, so CAD tools will need to handle an ever-growing percentage of all the wires in order to keep designer workloads constant. Global wires present a more serious problem to designers. These are wires that do not scale in length since they communicate signals across the chip. The delay of these wives will remain constant if repeaters are used meaning that relative to gate delays, their delays scale upwards. These increased delays for global communication will drive architectures toward modular designs with explicit global latency mechanisms.

The future of wires

Steep subthreshold swing transistors based on interband tunneling are examined toward extending the performance of electronics systems. In particular, this review introduces and summarizes progress in the development of the tunnel field-effect transistors (TFETs) including its origin, current experimental and theoretical performance relative to the metal-oxide-semiconductor field-effect transistor (MOSFET), basic current-transport theory, design tradeoffs, and fundamental challenges. The promise of the TFET is in its ability to provide higher drive current than the MOSFET as supply voltages approach 0.1 V.

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Low-Voltage Tunnel Transistors for Beyond CMOS Logic

Dielectric constant /spl epsi//sub r/ and broadband dielectric loss tan /spl delta/ measurements were performed for the thermoplastic toughened cyanate ester printed circuit board CYTUF material. Characterization of tan /spl delta/ over the 1-8 GHz frequency range was made using a simple short-pulse propagation technique. All the measurements were taken on four-metal-layer, 23/spl times/36 cm cards with representative transmission line structures. It was found the /spl epsi//sub r/=3.48-3.64 and tan /spl delta/=0.0095-0.01, which are much lower than for standard FR-4 material. The impact of improved characteristics on wireability is analyzed through simulations of representative printed circuit board interconnections.

Broadband characterization of low dielectric constant and low dielectric loss CYTUF cyanate ester printed circuit board material

A process of providing an external wiring and connecting package for a semiconductor chip wherein the chip is a major contributor to the strength of the package. External contacts and wiring are provided by a multilayer wiring member that may include a mesh ground plane with embedded power bus layer over a conductor layer for expansion mismatch control and impedance control, a protective encapsulation covers the bonds from the wiring conductors to the chip, and external contact connections employ fused metal through the contact members.

Process of multilayer conductor chip packaging

A clock signal distribution system is disclosed for providing synchronous clock signals to a plurality of electronic circuit devices. The system includes a clock signal generator means for providing a single frequency sinusoidal clock signal output and a plurality of electronic circuit devices. A clock signal distribution network including interconnected resonant segments of a transmission line 13 connected to the clock signal of the clock signal generator and to the plurality of electronic circuit devices for providing separate synchronous, phase aligned clock signals to the electronic circuit devices. The transmission line segments have lengths matched to the clock signal frequency wavelengths to eliminate clock signal distribution problems such as skew, jitter and pulse distortions.

Sinusoidal clock signal distribution using resonant transmission lines

A system, method and computer program product for supporting system initiated checkpoints in high performance parallel computing systems and storing of checkpoint data to a non-volatile memory storage device. The system and method generates selective control signals to perform checkpointing of system related data in presence of messaging activity associated with a user application running at the node. The checkpointing is initiated by the system such that checkpoint data of a plurality of network nodes may be obtained even in the presence of user applications running on highly parallel computers that include ongoing user messaging activity. In one embodiment, the non-volatile memory is a pluggable flash memory card.

Non-volatile memory for checkpoint storage

This presentation reviews current on-chip wiring design practices and the fundamental properties of on-chip lossy transmission lines. The deficiencies of RC-circuit representation are highlighted and it is shown that many of the modeling and simulation techniques developed for package interconnections must be adopted by microprocessor designers in order to achieve GHz clock rates.

Paul W. Coteus

Papers

Broadband characterization of low dielectric constant and low dielectric loss CYTUF cyanate ester printed circuit board material

Process of multilayer conductor chip packaging

Sinusoidal clock signal distribution using resonant transmission lines

Non-volatile memory for checkpoint storage

On-chip wiring design challenges for GHz operation