Three parallel algorithms for classical molecular dynamics are presented. The first assigns each processor a fixed subset of atoms; the second assigns each a fixed subset of inter-atomic forces to compute; the third assigns each a fixed spatial region. The algorithms are suitable for molecular dynamics models which can be difficult to parallelize efficiently—those with short-range forces where the neighbors of each atom change rapidly. They can be implemented on any distributed-memory parallel machine which allows for message-passing of data between independently executing processors. The algorithms are tested on a standard Lennard-Jones benchmark problem for system sizes ranging from 500 to 100,000,000 atoms on several parallel supercomputers--the nCUBE 2, Intel iPSC/860 and Paragon, and Cray T3D. Comparing the results to the fastest reported vectorized Cray Y-MP and C90 algorithm shows that the current generation of parallel machines is competitive with conventional vector supercomputers even for small problems. For large problems, the spatial algorithm achieves parallel efficiencies of 90% and a 1840-node Intel Paragon performs up to 165 faster than a single Cray C9O processor. Trade-offs between the three algorithms and guidelines for adapting them to more complex molecular dynamics simulations are also discussed.

Fast parallel algorithms for short-range molecular dynamics

Today's data centers may contain tens of thousands of computers with significant aggregate bandwidth requirements. The network architecture typically consists of a tree of routing and switching elements with progressively more specialized and expensive equipment moving up the network hierarchy. Unfortunately, even when deploying the highest-end IP switches/routers, resulting topologies may only support 50% of the aggregate bandwidth available at the edge of the network, while still incurring tremendous cost. Non-uniform bandwidth among data center nodes complicates application design and limits overall system performance.In this paper, we show how to leverage largely commodity Ethernet switches to support the full aggregate bandwidth of clusters consisting of tens of thousands of elements. Similar to how clusters of commodity computers have largely replaced more specialized SMPs and MPPs, we argue that appropriately architected and interconnected commodity switches may deliver more performance at less cost than available from today's higher-end solutions. Our approach requires no modifications to the end host network interface, operating system, or applications; critically, it is fully backward compatible with Ethernet, IP, and TCP.

/pdf/a-scalable-commodity-data-center-network-architecture-5evikm9tu4.pdf

A scalable, commodity data center network architecture

Power dissipation is a fundamental problem for nanoelectronic circuits. Scaling the supply voltage reduces the energy needed for switching, but the field-effect transistors (FETs) in today's integrated circuits require at least 60 mV of gate voltage to increase the current by one order of magnitude at room temperature. Tunnel FETs avoid this limit by using quantum-mechanical band-to-band tunnelling, rather than thermal injection, to inject charge carriers into the device channel. Tunnel FETs based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction over complementary metal-oxide-semiconductor (CMOS) transistors, so integrating tunnel FETs with CMOS technology could improve low-power integrated circuits.

Tunnel field-effect transistors as energy-efficient electronic switches

Concern about the performance of wires wires in scaled technologies has led to research exploring other communication methods. This paper examines wire and gate delays as technologies migrate from 0.18-/spl mu/m to 0.035-/spl mu/m feature sizes to better understand the magnitude of the the wiring problem. Wires that shorten in length as technologies scale have delays that either track gate delays or grow slowly relative to gate delays. This result is good news since these "local" wires dominate chip wiring. Despite this scaling of local wire performance, computer-aided design (CAD) tools must still become move sophisticated in dealing with these wires. Under scaling, the total number of wires grows exponentially, so CAD tools will need to handle an ever-growing percentage of all the wires in order to keep designer workloads constant. Global wires present a more serious problem to designers. These are wires that do not scale in length since they communicate signals across the chip. The delay of these wives will remain constant if repeaters are used meaning that relative to gate delays, their delays scale upwards. These increased delays for global communication will drive architectures toward modular designs with explicit global latency mechanisms.

The future of wires

Steep subthreshold swing transistors based on interband tunneling are examined toward extending the performance of electronics systems. In particular, this review introduces and summarizes progress in the development of the tunnel field-effect transistors (TFETs) including its origin, current experimental and theoretical performance relative to the metal-oxide-semiconductor field-effect transistor (MOSFET), basic current-transport theory, design tradeoffs, and fundamental challenges. The promise of the TFET is in its ability to provide higher drive current than the MOSFET as supply voltages approach 0.1 V.

/pdf/low-voltage-tunnel-transistors-for-beyond-cmos-logic-3w5c8knrc5.pdf

Low-Voltage Tunnel Transistors for Beyond CMOS Logic

5n7 A method is described for aligning a contact pattern on an electronic device held by a first movable support, with a bond site pattern on a lead frame held by a second movable support. The method includes the steps of: (a) creating and storing models of a chip's contact pattern and a lead frame's bond site pattern; (b) imaging the electronic device and lead frame; (c) determining the position of contacts on said electronic device and reorienting the contact pattern model to a best fit with the imaged contact position; (d) determining the position of each bond site on the imaged lead frame and reorienting the bond site model to a best fit with the imaged bond site position; (e) determining positional differences between the reoriented lead frame and contact pattern models; and (f) generating signals to reorient the first and second movable supports to minimize the positional differences when they are moved into a bonding position. A machine is described for performing the above method wherein each of three main movable elements of the machine is assigned a dimensional axis in which its travel is non-adjustable, so that other movable elements can be calibrated thereagainst.

System and method for inspection and alignment of semiconductor chips and conductive lead frames

A memory chip comprises an internal voltage regulator that is selectively enabled/disabled to regulate an external voltage used by the memory chip subunit.

Voltage regulator bypass in memory device

This paper compares several differential cable characteristics that were evaluated for multi-Gb/s data-rates for both data and clock paths for 1-10 m lengths. Time-domain measurements are shown for the unassembled and connectorized cables and for representative card-plus-cable signal paths and the performance limiting factors are highlighted. Techniques are shown for developing coupled-line models for odd and even excitations for all the components in a full chip-to-chip path in order to make realistic data-rate predictions.

https://www.researchgate.net/profile/Alina_Deutsch/publication/3423384_Characterization_and_performance_evaluation_of_differential_shielded_cables_for_multi-Gbs_data-rates/links/54bd0b4b0cf218da93909ebe.pdf

Characterization and performance evaluation of differential shielded cables for multi-Gb/s data-rates

Precast curable thermal interface adhesives facilitating the easy and repeatable separation and remaining of electronic components at thermal interfaces thereof, and a method for implementing the foregoing repeatable separation and remating at the thermal interfaces of components through the use of such adhesives.

Precast thermal interface adhesive for easy and repeated, separation and remating

A processor-implemented method for improving efficiency of a static core turn-off in a multi-core processor with variation, the method comprising: conducting via a simulation a turn-off analysis of the multi-core processor at the multi-core processor's design stage, wherein the turn-off analysis of the multi-core processor at the multi-core processor's design stage includes a first output corresponding to a first multi-core processor core to turn off; conducting a turn-off analysis of the multi-core processor at the multi-core processor's testing stage, wherein the turn-off analysis of the multi-core processor at the multi-core processor's testing stage includes a second output corresponding to a second multi-core processor core to turn off; comparing the first output and the second output to determine if the first output is referring to the same core to turn off as the second output; outputting a third output corresponding to the first multi-core processor core if the first output and the second output are both referring to the same core to turn off.

Paul W. Coteus

Papers

System and method for inspection and alignment of semiconductor chips and conductive lead frames

Voltage regulator bypass in memory device

Characterization and performance evaluation of differential shielded cables for multi-Gb/s data-rates

Precast thermal interface adhesive for easy and repeated, separation and remating

Efficiency of static core turn-off in a system-on-a-chip with variation