Most of the signal processing that we will study in this course involves local operations on a signal, namely transforming the signal by applying linear combinations of values in the neighborhood of each sample point. You are familiar with such operations from Calculus, namely, taking derivatives and you are also familiar with this from optics namely blurring a signal. We will be looking at sampled signals only. Let's start with a few basic examples. Local difference Suppose we have a 1D image and we take the local difference of intensities, DI(x) = 1 2 (I(x + 1) − I(x − 1)) which give a discrete approximation to a partial derivative. (We compute this for each x in the image.) What is the effect of such a transformation? One key idea is that such a derivative would be useful for marking positions where the intensity changes. Such a change is called an edge. It is important to detect edges in images because they often mark locations at which object properties change. These can include changes in illumination along a surface due to a shadow boundary, or a material (pigment) change, or a change in depth as when one object ends and another begins. The computational problem of finding intensity edges in images is called edge detection. We could look for positions at which DI(x) has a large negative or positive value. Large positive values indicate an edge that goes from low to high intensity, and large negative values indicate an edge that goes from high to low intensity. Example Suppose the image consists of a single (slightly sloped) edge:

http://ieeexplore.ieee.org/iel5/5/31307/01456462.pdf

Linear systems

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Design Of Analog Cmos Integrated Circuits

We provide a comprehensive overview of mathematical models and analytical techniques for millimeter wave (mmWave) cellular systems. The two fundamental physical differences from conventional sub-6-GHz cellular systems are: 1) vulnerability to blocking and 2) the need for significant directionality at the transmitter and/or receiver, which is achieved through the use of large antenna arrays of small individual elements. We overview and compare models for both of these factors, and present a baseline analytical approach based on stochastic geometry that allows the computation of the statistical distributions of the downlink signal-to-interference-plus-noise ratio (SINR) and also the per link data rate, which depends on the SINR as well as the average load. There are many implications of the models and analysis: 1) mmWave systems are significantly more noise-limited than at sub-6 GHz for most parameter configurations; 2) initial access is much more difficult in mmWave; 3) self-backhauling is more viable than in sub-6-GHz systems, which makes ultra-dense deployments more viable, but this leads to increasingly interference-limited behavior; and 4) in sharp contrast to sub-6-GHz systems cellular operators can mutually benefit by sharing their spectrum licenses despite the uncontrolled interference that results from doing so. We conclude by outlining several important extensions of the baseline model, many of which are promising avenues for future research.

Modeling and Analyzing Millimeter Wave Cellular Systems

The combination of millimeter-wave communications, arrays with a massive number of antennas, and small cell geometries is a symbiotic convergence of technologies that has the potential to dramatically improve wireless access and throughput. This article outlines the benefits, challenges, and potential solutions associated with cellular networks that incorporate these technologies.

Millimeter-wave massive MIMO: the next wireless revolution?

IEEE transactions on computer-aided design of integrated circuits and systems : a publication of the IEEE Circuits and Systems Society

This paper presents a 210-GHz transceiver with OOK modulation in a 32-nm SOI CMOS process (fT/fmax= 250/320 GHz). The transmitter (TX) employs a 2 × 2 spatial combining array consisting of a double-stacked cross-coupled voltage controlled oscillator (VCO) at 210 GHz with an on-off-keying (OOK) modulator, a power amplifier (PA) driver, a novel balun-based differential power distribution network, four PAs, and an on-chip 2 × 2 dipole antenna array. The noncoherent receiver (RX) utilizes a direct detection architecture consisting of an on-chip antenna, a low-noise amplifier (LNA), and a power detector. The VCO generates measured -13.5-dBm output power, and the PA shows a measured 15-dB gain and 4.6-dBm Psat. The LNA exhibits a measured in-band gain of 18 dB and minimum in-band noise figure (NF) of 11 dB. The TX achieves an EIRP of 5.13 dBm at 10 dB back-off from saturated power. It achieves an estimated EIRP of 15.2 dBm when the PAs are fully driven. This is the first demonstration of a fundamental frequency CMOS transceiver at the 200-GHz frequency range.

A CMOS 210-GHz Fundamental Transceiver With OOK Modulation

Integration of multi-mode multi-band transceivers on a single chip will enable low-cost millimeter-wave systems for next-generation automotive radar sensors. The first dual-band millimeter-wave transceiver operating in the 22-29-GHz and 77-81-GHz short-range automotive radar bands is designed and implemented in 0.18-? m SiGe BiCMOS technology with fT/fmax of 200/180 GHz. The transceiver chip includes a dual-band low noise amplifier, a shared downconversion chain, dual-band pulse formers, power amplifiers, a dual-band frequency synthesizer and a high-speed highly-programmable baseband pulse generator. The transceiver achieves 35/31-dB receive gain, 4.5/8-dB double side-band noise figure, >60/30-dB cross-band isolation, -114/-100.4-dBc/Hz phase noise at 1-MHz offset, and 14.5/10.5-dBm transmit power in the 24/79-GHz bands. Radar functionality is also demonstrated using a loopback measurement. The 3.9 × 1.9-mm2 24/79-GHz transceiver chip consumes 0.51/0.615 W.

A single-chip dual-band 22-to-29GHz/77-to-81GHz BiCMOS transceiver for automotive radars

Phase-locked loops (PLL) in radio-frequency (RF) and mixed analog-digital integrated circuits (ICs) experience substrate coupling due to the simultaneous circuit switching and power/ground (P/G) noise which translate to a timing jitter. In this paper. an analysis of the PLL timing jitter due to substrate noise resulting from P/G noise and large-signal switching is presented. A general comprehensive stochastic model of the substrate and P/G noise sources in very large-scale integration (VLSI) circuits is proposed. This is followed by calculation of the phase noise of the constituent voltage-controlled oscillator (VCO) in terms of the statistical properties of substrate and P/G noise. The PLL timing jitter is then predicted in response to the VCO phase noise. Our mathematical method is utilized to study the jitter-induced P/G noise in a CMOS PLL, which is designed and simulated in a 0.25-/spl mu/m standard CMOS process. A comparison between the results obtained by our mathematical model and those obtained by HSPICE simulation prove the accuracy of the predicted model.

Analysis of the PLL jitter due to power/ground and substrate noise

In this paper, the systematic design and analysis of a CMOS performance-optimized distributed low-noise amplifier (DLNA) comprising bandwidth-enhanced cascode cells will be presented. Each cascode cell employs an inductor between the common-source and common-gate devices to enhance the bandwidth, while reducing the high-frequency input-referred noise. The noise analysis and optimization of the DLNA accurately accounts for the impact of thermal noise of line terminations and all device noise sources of each CMOS cascode cell including flicker noise, correlated gate-induced noise and channel thermal noise on the overall noise figure. A three-stage performance-optimized wideband DLNA has been designed and fabricated in a 0.18-mum SiGe process, where only MOS transistors were utilized. Measurements of the test chip show a flat noise figure of 2.9 dB, a forward gain of 8 dB, and input and output return losses below -12 dB and -10 dB, respectively, across the 7.5 GHz UWB band. The circuit exhibits an average IIP3 of -3.55 dBm. The 872 mum times 872 mum DLNA chip consumes 12 mA of current from a 1.8-V DC voltage.

/pdf/design-and-analysis-of-a-performance-optimized-cmos-uwb-4oyalc4uxp.pdf

Payam Heydari

Papers

Millimeter-wave massive MIMO: the next wireless revolution?

A CMOS 210-GHz Fundamental Transceiver With OOK Modulation

A single-chip dual-band 22-to-29GHz/77-to-81GHz BiCMOS transceiver for automotive radars

Analysis of the PLL jitter due to power/ground and substrate noise

Design and Analysis of a Performance-Optimized CMOS UWB Distributed LNA