Showing papers by "Peide D. Ye published in 2022"

Scaled indium oxide transistors fabricated using atomic layer deposition

Abstract: In order to continue to improve integrated circuit performance and functionality, scaled transistors with short channel lengths and low thickness are needed. But the further scaling of silicon-based devices and the development of alternative semiconductor channel materials that are compatible with current fabrication processes is challenging. Here we report atomic-layer-deposited indium oxide transistors with channel lengths down to 8 nm, channel thicknesses down to 0.5 nm and equivalent dielectric oxide thickness down to 0.84 nm. Due to the scaled device dimensions and low contact resistance, the devices exhibit high on-state currents of 3.1 A/mm at a drain voltage of 0.5 V and a transconductance of 1.5 S/mm at a drain voltage 1 V. Our devices are a promising alternative channel material for scaled transistors with back-end-of-line processing compatibility.

The resurrection of tellurium as an elemental two-dimensional semiconductor

Abstract: Abstract The graphene boom has triggered a widespread search for novel elemental van der Waals materials thanks to their simplicity for theoretical modeling and easy access for material growth. Group VI element tellurium is an unintentionally p-type doped narrow bandgap semiconductor featuring a one-dimensional chiral atomic structure which holds great promise for next-generation electronic, optoelectronic, and piezoelectric applications. In this paper, we first review recent progress in synthesizing atomically thin Te two-dimensional (2D) films and one-dimensional (1D) nanowires. Its applications in field-effect transistors and potential for building ultra-scaled Complementary metal–oxide–semiconductor (CMOS) circuits are discussed. We will also overview the recent study on its quantum transport in the 2D limit and progress in exploring its topological features and chiral-related physics. We envision that the breakthrough in obtaining high-quality 2D Te films will inspire a revisit of the fundamental properties of this long-forgotten material in the near future.

Positive Bias Temperature Instability and Hot Carrier Degradation of Back-End-of-Line, nm-Thick, In2O3 Thin-Film Transistors

Abstract: Recently, back-end-of-line (BEOL) compatible indium oxide (In₂O₃) thin-film transistors (TFTs), grown by atomic layer deposition (ALD) with channel thickness of ~1 nm and channel length down to 40 nm, have achieved a record high drain current of 2.2 A/mm at ${V}_{\textit {DS}}$ of 0.7 V. A systematic characterization of the reliability issues, such as positive bias temperature stress (PBTS) and hot carrier degradation (HCD), would allow its immediate integration into innovative ICs, such as 3D-stacked SRAM or on-chip bridge for mixed-voltage systems. Surprisingly, PBTS and HCD are both characterized by a universal two-stage threshold voltage shift ( $\Delta \!{V}_{\textit {th}}$ , a positive shift followed by a temperature-activated negative shift). This is attributed respectively to electron trapping/trap-generation and hydrogen-assisted formation of donor-traps. These competing mechanisms of $\Delta ~{V}_{\textit {th}}$ depend on the stress voltages and stress temperature. Unlike traditional logic transistors, HCD in BEOL-TFTs is strongly correlated to PBTS, caused by the much stronger vertical field in an ultra-thin device. Overall, this high-performance BEOL-transistor is remarkably reliable, with a relatively small $\Delta ~{V}_{\textit {th}}$ under PBTS/HCD stress conditions at room temperature (RT). However, self- and mutual heating of BEOL interconnect levels and the resultant threshold voltage variability must be mitigated/managed for its successful integration in various neuromorphic circuits.

Enhancement of Thermal Transfer From β-Ga2O3 Nano-Membrane Field-Effect Transistors to High Thermal Conductivity Substrate by Inserting an Interlayer

Abstract: The role of a HfO₂ or ZrO₂ interlayer as a thermal bridge between a $\beta $ -Ga₂O₃ channel and a sapphire substrate was investigated using a $\beta $ -Ga₂O₃ nano-membrane FET as a test vehicle. A 35% less channel temperature increase was observed when a thin HfO₂ or ZrO₂ interlayer was inserted between the $\beta $ -Ga₂O₃ channel and the sapphire substrate compared to devices without interlayers. Phonon density of states (PDOS) mismatch can explain the improvement of the thermal boundary conductance (TBC). In the acoustic region, the PDOS of HfO₂ or ZrO₂ has about a 700% larger overlap area with the PDOS of $\beta $ -Ga₂O₃ compared to the PDOS of sapphire. This suggests that the insertion of a thermal bridge interlayer can provide a potential solution to the low thermal conductivity of $\beta $ -Ga₂O₃ and the self-heating effect of $\beta $ -Ga₂O₃-based FETs.

Ultra-Fast Operation of BEOL-Compatible Atomic-Layer-Deposited In2O3 Fe-FETs: Achieving Memory Performance Enhancement with Memory Window of 2.5 V and High Endurance > 109 Cycles without VT Drift Penalty

Abstract: In this work, we report the ultra-fast operation of back-end-of-line (BEOL) compatible Fe-FETs with atomic layer deposition (ALD) In2O3 and HfZrO2 (HZO) as channel semiconductor and ferroelectric gate insulator with channel length (Lch) scaled down to 7 nm, enabled by ultra-fast I-V (UFIV) and pulse I-V measurements. It is found that device memory characteristics benefit from fast operation down to 10 ns level, by a suppression of trapping effect while maintaining fast FE switching speed. High memory performance is achieved, exhibiting a wide memory window of 2.5 V and a high endurance exceeding 109 cycles without VT drift penalty. These results suggest that oxide semiconductor Fe-FETs are promising toward monolithic 3D integration for in-memory computing at ultra-fast operation speed.

Thermal Studies of BEOL-compatible Top-Gated Atomically Thin ALD In2O3 FETs

Abstract: In this work, we investigate the thermal issues of top-gated (TG), ultrathin, atomic layer deposition (ALD) grown, back-end-of-line (BEOL) compatible indium oxide (In2O3) transistors by observation and visualization of the self-heating effect (SHE) using high-resolution thermo-reflectance (TR) measurement. SHE is alleviated by highly resistive silicon (HR Si) substrate with high thermal conductivity (κSi). The increased temperature (ΔT) of the devices on HR Si substrate is roughly 6 times lower than that with SiO2/Si substrate. Furthermore, thermal simulation with a finite-element method exhibits exceptional agreement to ΔT distribution with experimental results. By thermal engineering, TG In2O3 transistors with channel thickness (Tch) of 1.8 nm and high drain current (ID) up to 2.65 mA/µm are achieved.

Characterization of Interface and Bulk Traps in Ultrathin Atomic Layer-Deposited Oxide Semiconductor MOS Capacitors With HfO2/In2O3 Gate Stack by C-V and Conductance Method

Abstract: Oxide semiconductors have attracted revived interest for complementary metal–oxide–semiconductor (CMOS) back-end-of-line (BEOL) compatible devices for monolithic 3-dimensional (3D) integration. To obtain a high-quality oxide/semiconductor interface and bulk semiconductor, it is critical to enhance the performance of oxide semiconductor transistors. Atomic layer-deposited (ALD) indium oxide (In2O3) has been reported with superior performance such as high drive current, high mobility, steep subthreshold slope, and ultrathin channel. In this work, the interface and bulk traps in the MOS gate stack of ALD In2O3 transistors are systematically studied by using the C–V and conductance method. A low EOT of 0.93 nm is achieved directly from the accumulation capacitance in C–V measurement, indicating a high-quality gate oxide and oxide/semiconductor interface. Defects in bulk In2O3 with energy levels in the subgap are confirmed to be responsible for the conductance peak in GP/ω versus ω curves by TCAD simulation of C–V and G–V characteristics. A high n-type doping of 1×1020/cm3 is extracted from C–V measurement. A high subgap density of states (DOS) of 3.3×1020 cm−3 eV−1 is achieved using the conductance method, which contributes to the high n-type doping and high electron density. The high n-type doping further confirms the capability of channel thickness scaling because the charge neutrality level aligns deeply inside the conduction band.

Fluorine-passivated In2O3 thin film transistors with improved electrical performance via low-temperature CF4/N2O plasma

Abstract: In this Letter, we report the electrical performance improvement of indium oxide (In2O3) thin film transistors (TFTs) via a low-temperature CF4/N2O plasma treatment. It is found that the fluorination via CF4/N2O plasma can reduce the excessive electrons in the In2O3 channel more effectively compared to the oxidative annealing, providing the same low off-currents at a lower temperature of 200 °C, while the hydrogenation could not give rise to the off-current reduction. The fluorinated In2O3 TFTs with a channel thickness of 3.5 nm, a HfO2 dielectric thickness of 3.5 nm, and a channel length ranging from 80 nm to 1 μm demonstrate markedly improved electrical performances, including a high field effect mobility of 72.8 cm2/V s, a more positive threshold voltage, a higher on/off current ratio of ∼106, a smaller subthreshold swing below 200 mV/dec, and a higher stability to both negative and positive gate biases. X-ray photoelectron spectroscopy (XPS) confirms the fluorine incorporation in In2O3/HfO2 heterojunction upon CF4/N2O plasma, speculatively passivating the oxygen vacancies and explaining TFT performance enhancement. This study suggests that the anion doping such as fluorine incorporation could be an effective method to improve the performance of oxide semiconductor TFTs with ultrathin channel and dielectric.

Nanometer-Thick Oxide Semiconductor Transistor with Ultra-High Drain Current.

Abstract: High drive current is a critical performance parameter in semiconductor devices for high-speed, low-power logic applications or high-efficiency, high-power, high-speed radio frequency (RF) analogue applications. In this work, we demonstrate an In2O3 transistor grown by atomic layer deposition (ALD) at back-end-of-line (BEOL) compatible temperatures with a record high drain current in planar FET, exceeding 10 A/mm, the performance of which is 2-3 times better than all known transistors with semiconductor channels. A high transconductance reaches 4 S/mm, recorded among all transistors with a planar structure. Planar FETs working ballistically or quasi-ballistically are exploited as one of the simplest platforms to investigate the intrinsic transport properties. It is found experimentally and theoretically that a high carrier density and high electron velocity both contribute to this high on-state performance in ALD In2O3 transistors, which is made possible by the high-quality oxide/oxide interface, the metal-like charge-neutrality-level (CNL) alignment, and the high band velocities induced by the low density-of-state (DOS). Experimental Hall, I-V, and split C-V measurements at room temperature confirm a high carrier density of up to 6-7 × 1013 /cm2 and a high velocity of about 107 cm/s, well-supported by density functional theory (DFT) calculations. The simultaneous demonstration of such high carrier concentration and average band velocity is enabled by the exploitation of the ultrafast pulse scheme and heat dissipation engineering.

A Gate-All-Around inO Nanoribbon FET With Near 20 mA/m Drain Current

Abstract: In this work, we demonstrate atomic-layer-deposited (ALD) single-channel indium oxide (In2O3) gate-all-around (GAA) nanoribbon field-effect transistors (FETs) in a back-end-of-line (BEOL) compatible process. A maximum on-state current (ION) of 19.3 mA/ $\mu \text{m}$ (near 20 mA/ $\mu \text{m}$ ) and an on/off ratio of 106 are achieved in an In2O3 GAA nanoribbon FET with a channel thickness (TIO) of 3.1 nm, channel length (Lch) of 40 nm, channel width (Wch) of 30 nm and dielectric HfO2 of 5 nm. Short-pulse measurements are applied to mitigate the self-heating effect induced by the ultra-high drain current flowing in the ultra-thin channel layer. The record high drain current obtained from an In2O3 FET is about one order of magnitude higher than any conventional single-channel semiconductor FETs. This extraordinary drain current and its related on-state performance demonstrate that ALD In2O3 is a promising oxide semiconductor channel with great opportunities in BEOL compatible monolithic 3D integration.

Ultrathin two-dimensional van der Waals asymmetric ferroelectric semiconductor junctions

Abstract: Two-dimensional van der Waals ferroelectric semiconductors have attracted extensive research interest in both theoretical investigation and device applications due to their ferroelectricity and semiconducting nature. However, it is still not well understood how the ferroelectric phase is able to coexist with the semiconducting phase in this emerging material class. In this work, mm-scale continuous films of In2Se3 with a thickness of ∼3 nm were synthesized successfully by physical vapor deposition. Furthermore, we fabricated asymmetric ferroelectric semiconductor junctions (a-FSJs) from thick exfoliated and PVD-grown ultrathin In2Se3 films. A high read current density of ∼100 A/cm2 and a distinction ratio of over 102 at VRead = 0.5 V are achieved in devices fabricated by a 3 nm-thick In2Se3 film toward ultrahigh-density memory integration. Notably, the coercive voltage is constant, with In2Se3 film thickness decreasing from 200 to 3 nm. A qualitative model is proposed to elucidate the anomalous film-thickness-independent coercive voltage in this ultrathin a-FSJ, which can also be generalized to other emerging two-dimensional ferroelectric semiconductors.

Vertically stacked multilayer atomic-layer-deposited sub-1-nm In2O3 field-effect transistors with back-end-of-line compatibility

Abstract: In this work, we demonstrate vertically stacked multilayer sub-1-nm In2O3 field-effect transistors (FETs) with surrounding gate in a back-end-of-line (BEOL) compatible low-temperature fabrication process. A typical bottom-gated single layer In2O3 FET with maximum on-state current (ION) of 890 μA/ μm at VDS = 0.8 V and an on/off ratio over 106 is achieved with a channel length (Lch) of 100 nm. The effects of HfO2 capping and O2 annealing are systematically studied, which is critical to realizing the multilayer FETs. Each atomically thin In2O3 channel layer with a thickness (TIO) of 0.9 nm is realized by atomic layer deposition (ALD) at 225 °C. Multilayer FETs with a number of In2O3 layers up to 4 and 1.2 nm-thick HfO2 between each individual layer are fabricated. An enhancement of on-state current (ION) from 183 μA in a single layer In2O3 FET to 339 μA in a 4 layer device with an on/off ratio of 3.4 × 104 is achieved, demonstrating the key advantage of the multilayer FETs to improve the current. Several critical features, such as large-area growth, high uniformity, high reproducibility, ultrathin body, flexibility, and BEOL compatibility, have turned ALD In2O3 into a noteworthy candidate for next-generation oxide semiconductor channel materials.

Controlling Threshold Voltage of CMOS SOI Nanowire FETs With Sub-1 nm Dipole Layers Formed by Atomic Layer Deposition

Abstract: In this article, bidirectional control of threshold voltage ( ${V}_{T}$ ) is realized in both n- and p-silicon-on-insulator (SOI) nanowire FETs (NWFETs) by using sub-1 nm atomic-layer-deposited (ALD) dipole layers (Y₂O₃ and Al₂O₃) for the first time. A 0.7 nm Y₂O₃ inserted between bottom native SiO_x (< 1 nm) and top HfO₂ (3 nm) can shift the ${V}_{\text {TH}}$ by −138 and −58 mV for n- and p-NWFET, respectively, while 0.7 nm Al₂O₃ can shift the ${V}_{T}$ of n-NWFET by +219 mV and p-NWFET by +134 mV. The tunability of such a high-k superstructure for the flat band voltage ( ${V}_{\text {FB}}$ ) shift of capacitors and ${V}_{\text {TH}}$ shift of planar n-SOI FETs are also investigated. Furthermore, to concisely control the ${V}_{\text {TH}}$ and ${V}_{\text {FB}}$ as design, capacitors fabricated with quadra-layer (SiO_x/HfO₂/Al₂O₃/Y₂O₃) high-k superstructure were fabricated and 3 mV ${V}_{\text {FB}}$ shift is achieved by carefully adjusting the composition of intermixed-dipole layers. This work points out the route to concisely tune the threshold voltage of complementary metal-oxide-semiconductor (CMOS) FETs with the desired direction and strength.

Improved Stability With Atomic-Layer-Deposited Encapsulation on Atomic-Layer In2O3 Transistors by Reliability Characterization

Abstract: Ultrathin In2O3 and other recently explored low-thermal-budget ultrathin oxide semiconductors have shown great promise for back-end-of-line (BEOL)-compatible logic layers and monolithic 3-D (M3-D) integration. However, the long-term stability and reliability of these defect-rich atomically thin channels have not been intensively explored yet. Here, we present a study of the long-term reliability of transistors with 1.2-nm-thick atomic-layer-deposited (ALD)-grown In2O3 channels by room-temperature positive bias instability (PBI) and negative bias instability (NBI) experiments. The observed behavior can be largely explained by a trap neutrality level (TNL) model. A route to reduce the parameter drift has been developed using encapsulation in sequence with ${V}_{T}$ engineering by an O2 plasma treatment. After treatment, the magnitude of long-term ${V}_{T}$ shift is reduced for both positive and negative gate bias stresses, and for negative bias stress, other transistor parameters are stabilized as well. In all cases, the subthreshold swing (SS) does not change over time, suggesting that stress-induced interface defects form far below the conduction band, if at all.

First Demonstration of BEOL-Compatible Ultrathin AtomicLayer-Deposited InZnO Transistors with GHz Operation and Record High Bias-Stress Stability

Abstract: This work reports for the first time ultrathin atomic-layer-deposited (ALD) InZnO as a novel back-end-of line (BEOL) channel material for monolithic 3D integration. By tuning the ratio of In to Zn with ALD cycles, InZnO transistors with 3.5 nm channel thickness can achieve excellent subthreshold swings (SS) as low as 65 mV/dec, high on-off current ratio up to $10 ^{11}$, and sizeable on-current density (ION) up to 1.33 A/mm for In-rich channels at 100 nm channel length with drain voltage (VDS) of 1 V. A surprising high degree of stability under large positive gate bias stress (statistically measured threshold voltage shift $\Delta \mathrm{V}_{T}$ of -16 mV after 1500 s stress with gate voltage bias (VBias) of 3.5 V) is observed in the In:Zn $=1$:1 case. ALD process resolves the long-time concern on the stability of sputtered InZnO films as the channels without Ga doping. A charge-neutrality-level (CNL) alignment and trap generation model is proposed to explain this unique phenomenon of negligible VT shift under positive gate bias stress (PBS). Finally, ground-signal-ground (GSG) structures are also fabricated to investigate the RF performance of these BEOL-compatible transistors with GHz operation frequencies.

Tunable nonreciprocal electrical transport in 2D Tellurium with different chirality

Abstract: 1School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47907, United States. 2Birck Nanotechnology Center, Purdue University, West Lafayette, IN 47907, United States. 3School of Industrial Engineering, Purdue University, West Lafayette, IN 47907, United States. 4School of Materials Science and Engineering, Purdue University, West Lafayette, Indiana 47907, United States.

Optical-feedback cavity ring-down spectroscopy for NO2 extinction coefficient measurement using a continuous wave laser diode.

Abstract: Optical-feedback (OF) cavity ring-down spectroscopy consisting of a linear cavity is developed by employing a continuous wave laser diode (LD) with multi-longitudinal modes. Due to the OF effect caused by the cavity output laser back into the LD, the laser frequency is locked, and the intracavity laser intensity is enhanced. We use different concentrations of NO2 gases to test the apparatus, and the results show good agreement with theoretical values. Owing to the compactness of the laser source and high detection accuracy, the device can be used for detection of low-concentration absorbent gases in the environmental monitoring field.

Determination of Domain Wall Velocity and Nucleation Time by Switching Dynamics Studies of Ferroelectric Hafnium Zirconium Oxide

Abstract: In this work, we present the first experimental determination of nucleation time and domain wall (DW) velocity by studying switching dynamics of ferroelectric (FE) hafnium zirconium oxide (HZO). Experimental data and simulation results were used to quantitatively study the switching dynamics. The switch speed is degraded in high aspect ratio devices due to the longer DW propagation time or with dielectric interfacial layer due to the required additional tunneling and trapping time by the leakage current assist switch mechanism.

Monolithic 3D Integration of Vertically Stacked CMOS Devices and Circuits with High-Mobility Atomic-Layer-Deposited In2O3 n-FET and Polycrystalline Si p-FET: Achieving Large Noise Margin and High Voltage Gain of 134 V/V

Abstract: In this work, we demonstrate the monolithic 3D integration (M3D) of vertically stacked p-type low-temperature polycrystalline silicon (LTPS) top-gate transistor and n-type back gate oxide semiconductor transistor, similar to a complementary field-effect transistor (CFET) structure, for complementary metal-oxide-semiconductor (CMOS) logic applications, with a low thermal budget of 450°C. High-performance logic devices and circuits (inverter, NAND, NOR) are demonstrated with a high voltage gain of 134.3 V/V and a large noise margin of 0.84 V at VDD of 2 V, which are among the best values in reported CMOS inverters by oxide semiconductor n-FET and LTPS p-FET. These devices are enabled by a high electron mobility atomic-layer deposited (ALD) In2O3 as n-channel to balance the high hole mobility of LTPS. The fabricated ALD In2O3n - FETs exhibit high electron mobility $\gt 100$ cm $^{2} / V\cdot s$ on $\text{SiO}_{2}/\text{Si}$ substrate and mobility of 23.8 cm $^{2} /V\cdot s$ in the n-FET of the M3D CMOS inverter, which is the highest number in reported CMOS inverters with oxide semiconductor n-FETs and LTPS p-FETs.

BEOL-Compatible, ALD-grown In2O3 Top-Gate FETs with Maximum Drain Current of 3 A/mm through Thermal Engineering and Pulse Measurement

Abstract: This paper reports 1 A/mm drain current (ID) and 0.24 Ω•mm contact resistance (RC) at on-state with BEOL-compatible, top-gated, and ALD-grown 1.3-nm In2O3. Nonetheless, the devices suffer severely from self-heating effect (SHE) as larger bias is applied. Accordingly, beside quantitatively investigating the SHE in this system, thermal engineering is utilized to greatly alleviate it and therefore achieve higher ID of 2 A/mm by employing highly resistive silicon as the substrate. Moreover, pulse measurements further reduce SHE and attain even higher ID of 3 A/mm due to the lowered power rate of the devices.

Transient Thermal and Electrical Co-Optimization of BEOL Top-Gated ALD In₂O₃ FETs on Various Thermally Conductive Substrates Including Diamond

Abstract: In this work, we co-optimize the transient thermal and electrical characteristics of top-gated (TG), ultrathin, atomic-layer-deposited (ALD), back-end-of-line (BEOL) compatible indium oxide (In2 O3) transistors on various thermally conductive substrates by visualization of the self-heating effect (SHE) utilizing an ultrafast high-resolution (HR) thermo-reflectance (TR) imaging system and overcome the thermal challenges through substrate thermal management and short-pulse measurement. At the steady-state, the temperature increase $(\Delta \mathrm{T})$ of the devices on highly resistive silicon (HR Si) and diamond substrates are roughly 6 and 13 times lower than that on SiO $_{2} /$Si substrate, due to the higher thermal conductivities $(\kappa) $ of HR Si and diamond. Consequently, ultrahigh drain current (ID) of 3.7 mA$/ \mu \mathrm{m}$ at drain voltage (VDS) of 1.4 V with direct current (DC) measurement is achieved with TG ALD In2 O3 FETs on diamond substrate. Furthermore, transient thermal study shows that it takes roughly 350 and 300 ns for the devices to heat-up and cool-down to the steady-states, being independent on the substrate. The extracted time constants of heat-up $(\tau_{h})$ and cool-down $(\tau_{c})$ processes are 137 and 109 ns, respectively. By employing electrical short-pulse measurement with pulse width (tpulse) shorter than $\tau_{h}$, the SHE can be significantly reduced. Accordingly, a higher ID of 4.3 mA$/ \mu \mathrm{m}$ is realized with a 1.9nm-thick In2 O3 FET on HR Si substrate after co-optimization.

Atomic-layer-deposited Atomically Thin In2O3 Channel for BEOL Logic and Memory Applications

Abstract: Summary form only given, as follows. The complete presentation was not made available for publication as part of the conference proceedings. In this talk, we report on the first demonstration of atomically thin In 2 O 3 channel for logic and memory devices by a back-end-of-line (BEOL) compatible atomic layer deposition (ALD) process [1] , [2] . High performance planar In 2 O 3 transistors with high mobility of 113 cm 2 /V•s and record high maximum drain current of 2.5 mA/um are achieved by channel thickness engineering and post-deposition annealing. High-performance ALD In 2 O 3 based zero-V GS -load inverter is demonstrated with maximum voltage gain of 38 V/V and minimum supply voltage (V DD ) down to 0.5 V. ALD In 2 O 3 3D Fin transistors are also demonstrated, benefiting from the conformal deposition capability of ALD [3] . High-performance In 2 O 3 ferro-electric transistors are demonstrated using ALD HfZrO 2 gating with >2.2V large memory window, >10 years retention and >10 8 endurance [4] . These results suggest ALD oxide semiconductors and devices have unique advantages and are promising toward BEOL-compatible monolithic 3D integration.

Reliability of Atomic-Layer-Deposited Gate-All-Around In2O3 Nano-Ribbon Transistors with Ultra-High Drain Currents

Abstract: In this work, we systematically investigate the reliability of atomic-layer-deposited (ALD) gate-all-around (GAA) single-channel In2 O3 nano-ribbon field-effect transistors (FETs) with 5 nm HfO2 gate dielectric and a maximum on-state current (ION) approaching 20 mA/μm at drain voltage (VDS) of 1.7 V. A channel length (Lch) and channel width (Wch) independent positive threshold voltage (VT) shift under negative gate bias stress (NBS) and a negative VT shift under positive gate bias stress (PBS) are observed universally in all GAA In2 O3 FETs, which is opposite to bias instability of the conventional Si CMOS and IGZO thin film transistors (TFTs). This unusual behavior can be simply explained by the concept of the trap neutral level (TNL) which is deeply aligned inside the In2 O3 conduction band and the generation of donor-and acceptor-like traps in different gate bias stress conditions. In addition, other reliability issues including stress and recovery, gate bias dependence and temperature dependence are also studied. This comprehensive reliability analysis establishes ALD In2 O3 as a competitive channel material of the back-end-of-line (BEOL) compatible FETs for 3D monolithic integration into next generation ICs.

20‐3: Invited Paper: BEOL‐Compatible Ferroelectric Field‐Effect Transistors with Atomic Layer Deposition of Oxide Semiconductor Channel Toward Monolithic 3D Integration

Abstract: In this work, we report a BEOL-compatible ferroelectric field-effect transistor using oxide semiconductor as channel and ferroelectric hafnium zirconium oxide as gate insulator all grown by atomic layer deposition with a low thermal budget of 400°C, and meanwhile demonstrating well-behaved ferroelectric characteristics.

ZnO–ferromagnetic metal vertically aligned nanocomposite thin films for magnetic, optical and acoustic metamaterials

Abstract: Magnetoacoustic waves generated in piezoelectric and ferromagnetic coupled nanocomposite films through magnetically driven surface acoustic waves present great promise of loss-less data transmission. In this work, ferromagnetic metals of Ni, Co and CoxNi1−x are coupled with a piezoelectric ZnO matrix in a vertically-aligned nanocomposite (VAN) thin film platform. Oxidation was found to occur in the cases of ZnO–Co, forming a ZnO–CoO VAN, while only very minor oxidation was found in the case of ZnO–Ni VAN. An alloy approach of CoxNi1−x has been explored to overcome the oxidation during growth. Detailed microstructural analysis reveals limited oxidation of both metals and distinct phase separation between the ZnO and the metallic phases. Highly anisotropic properties including anisotropic ferromagnetic properties and hyperbolic dielectric functions are found in the ZnO–Ni and ZnO–CoxNi1−x systems. The magnetic metal–ZnO-based hybrid metamaterials in this report present great potential in coupling of optical, magnetic, and piezoelectric properties towards future magnetoacoustic wave devices.

Vertically stacked multilayer atomic-layer-deposited sub-1-nm In 2 O 3 field-effect transistors with back-end-of-line compatibility studied by

Abstract: In this work, we demonstrate vertically stacked multilayer sub-1-nm In 2 O 3 field-effect transistors (FETs) with surrounding gate in a back-end-of-line (BEOL) compatible low-temperature fabrication process. A typical bottom-gated single layer In 2 O 3 FET with maximum on-state current (I ON ) of 890 l A/ l m at V DS ¼ 0.8 V and an on/off ratio over 10 6 is achieved with a channel length (L ch ) of 100nm. The effects of HfO 2 capping and O 2 annealing are systematically studied, which is critical to realizing the multilayer FETs. Each atomically thin In 2 O 3 channel layer with a thickness (T IO ) of 0.9 nm is realized by atomic layer deposition (ALD) at 225 (cid:2) C. Multilayer FETs with a number of In 2 O 3 layers up to 4 and 1.2nm-thick HfO 2 between each individual layer are fabricated. An enhancement of on-state current (I ON ) from 183 l A in a single layer In 2 O 3 FET to 339 l A in a 4 layer device with an on/off ratio of 3.4 (cid:3) 10 4 is achieved, demonstrating the key advantage of the multilayer FETs to improve the current. Several critical features, such as large-area growth, high uniformity, high reproducibility, ultrathin body, flexibility, and BEOL compatibility, have turned ALD In 2 O 3 into a noteworthy candidate for next-generation oxide semiconductor channel materials.

2D or Not 2D: A Thermodynamic Approach to Modeling Space Solar Cells’ Efficiency with 2D Materials

Abstract: Approximately 3 billion people have never used the internet due to its costs and inaccessibility, particularly in developing countries. To provide these areas with affordable internet, reducing the cost of building and launching satellites has become paramount in the assessment of their design, particularly their solar cells. While three-dimensional semiconductor materials like gallium arsenide (GaAs) have been the main material used in these cells to convert solar energy into electrical energy, two-dimensional (2D) materials like tellurene have demonstrated properties that warrant consideration. This research evaluates the potential of a novel 7-junction space solar cell configuration consisting of manganese phosphorus trisulfide, tungsten disulfide, rhenium disulfide, molybdenum disulfide, molybdenum ditelluride, bismuth oxyselenide, and tellurene to replace current 3-junction configurations using GaAs-based materials. Thermodynamic expressions, including the efficiency of a Carnot heat engine and a geometric optimization approach using the Shockley-Queisser triangle, were analyzed to derive equations for two properties critical to a space solar cell: efficiency and specific power. Computational simulations were run, and the results indicate that a 7-junction space solar cell configuration using 2D materials can enable a maximum efficiency gain of 12%, a mass reduction by over one-fifth, and a specific power output improvement of 54% at lower costs compared to GaAs-based space solar cells. The implications of this study point to the performance and cost feasibility of satellite usage for a broad range of applications, with social and environmental significance.

Record RF Performance of Ultra-thin Indium Oxide Transistors with Buried-gate Structure

Abstract: Ultra-thin indium oxide (In2O3) from several nanometers to sub-nanometer thick has recently been revealed as an excellent n-type semiconductor channel material for back-end-of-line (BEOL) compatible transistors due to its low thermal budget, low subthreshold swing (SS), high on current and Ion/Ioff ratio, and high mobility [1]–[3]. However, a critical question that has not yet been addressed is that of the maximum frequency at which these devices can operate, which will play a deciding role in their analog applications. This work reports for the first time the detailed radio frequency (RF) characterization of some of these In2O3 RF transistors scaling down to 150 nm channel lengths.